Shrinking device size has been a major area of interest for VLSI design engineers. In order to achieve multiple functions on the same substrate using the standard technology, designers have to deal with the issues of area and power dissipation. So there is a pressing demand for designers to work in the area of optimization. In this paper, we propose to optimize a Wallace Tree multiplier. The multiplier was implemented at the circuit level of design abstraction with Virtuoso® tool in Cadence.

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Vlsi Power Dissipation Optimization Wallace Tree Multiplier Fpm Cadence