International Conference on Microelectronics, Circuits and Systems |
Foundation of Computer Science USA |
MICRO - Number 2 |
October 2014 |
Authors: Shefali Mamataj, Biswajit Das, Dibya Saha |
598f2444-bbc5-4b24-8354-c3d1223be6aa |
Shefali Mamataj, Biswajit Das, Dibya Saha . An Approach to Design Different Weighted Code Synchronous Counters by the Sequential Circuit Elements of Reversible Gates. International Conference on Microelectronics, Circuits and Systems. MICRO, 2 (October 2014), 9-16.
In recent years, reversible logic has emerged as a promising computing paradigm showing its applications in various fields like low power computing, quantum computing, nanotechnology, optical computing and DNA computing. This paper proposes different sequential circuit elements of reversible gates and its application in the designing of different weighted counters. These synchronous reversible counters provide the initial threshold to build the more complex system having reversible sequential circuits as a primitive component and which can execute more complicated operations using quantum computers. Since the output of a sequential circuit depends not only on the present inputs but also on the past input conditions, the construction of sequential elements using reversible logic gates is quite complex than that of a combinational circuit. This paper proposes reversible D flip flop, JK flip flop, T flip flop and also represents 4 bit BCD 8421 weighted code synchronous counter, 842'1' weighted code synchronous counter, 3321 weighted code synchronous counter and 4221 weighted code synchronous counter using the proposed reversible T flip flop . A comparison between these designs in terms of garbage output, number of gates, constant input and total logical calculation also has been made.