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Reseach Article

UART Designing for Four Different Baud Rate for Cyclone III Family

Published on May 2013 by Sunita Satyaram Yadav, Asha Durafe, Pratik Kanani
International Conference and Workshop on Emerging Trends in Technology 2014
Foundation of Computer Science USA
ICWET2014 - Number 2
May 2013
Authors: Sunita Satyaram Yadav, Asha Durafe, Pratik Kanani
268c125e-a611-440f-81e4-80e6983cc9f5

Sunita Satyaram Yadav, Asha Durafe, Pratik Kanani . UART Designing for Four Different Baud Rate for Cyclone III Family. International Conference and Workshop on Emerging Trends in Technology 2014. ICWET2014, 2 (May 2013), 30-33.

@article{
author = { Sunita Satyaram Yadav, Asha Durafe, Pratik Kanani },
title = { UART Designing for Four Different Baud Rate for Cyclone III Family },
journal = { International Conference and Workshop on Emerging Trends in Technology 2014 },
issue_date = { May 2013 },
volume = { ICWET2014 },
number = { 2 },
month = { May },
year = { 2013 },
issn = 0975-8887,
pages = { 30-33 },
numpages = 4,
url = { /proceedings/icwet2014/number2/16541-1437/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Proceeding Article
%1 International Conference and Workshop on Emerging Trends in Technology 2014
%A Sunita Satyaram Yadav
%A Asha Durafe
%A Pratik Kanani
%T UART Designing for Four Different Baud Rate for Cyclone III Family
%J International Conference and Workshop on Emerging Trends in Technology 2014
%@ 0975-8887
%V ICWET2014
%N 2
%P 30-33
%D 2013
%I International Journal of Computer Applications
Abstract

UART (Universal Asynchronous Receiver Transmitter) is used for short-distance, low speed, low-cost data exchange between computer and peripheral. They provide a means to send data with a minimum of wires. The data is sent bit-serially, and no clock signal is sent along with it. The fact that a clock is not transmitted with the data complicates the design of a UART. The two systems (sender and receiver) have separate, unsynchronized, clock signals. The programmable logic devices can be used for such application by developing core for UART. By using hardware descriptive language UART simulation can be tested before it can be loaded on programmable device. In this project we present UART which includes three modules which are the baud rate generator, receiver and transmitter.

References
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Index Terms

Computer Science
Information Sciences

Keywords

Uart Cyclone Iii vhdl four Baud Rates