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Low Power error Detector Design by using Low Power Flip Flops Logic

Published on May 2013 by Dibyalekha Chaini, Priyanka Malgi, Snehal Lopes
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International Conference and Workshop on Emerging Trends in Technology 2014
Foundation of Computer Science USA
ICWET2014 - Number 2
May 2013
Authors: Dibyalekha Chaini, Priyanka Malgi, Snehal Lopes
5da3f82f-2188-426c-a849-eb0d92826a52

Dibyalekha Chaini, Priyanka Malgi, Snehal Lopes . Low Power error Detector Design by using Low Power Flip Flops Logic. International Conference and Workshop on Emerging Trends in Technology 2014. ICWET2014, 2 (May 2013), 25-29.

@article{
author = { Dibyalekha Chaini, Priyanka Malgi, Snehal Lopes },
title = { Low Power error Detector Design by using Low Power Flip Flops Logic },
journal = { International Conference and Workshop on Emerging Trends in Technology 2014 },
issue_date = { May 2013 },
volume = { ICWET2014 },
number = { 2 },
month = { May },
year = { 2013 },
issn = 0975-8887,
pages = { 25-29 },
numpages = 5,
url = { /proceedings/icwet2014/number2/16540-1435/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Proceeding Article
%1 International Conference and Workshop on Emerging Trends in Technology 2014
%A Dibyalekha Chaini
%A Priyanka Malgi
%A Snehal Lopes
%T Low Power error Detector Design by using Low Power Flip Flops Logic
%J International Conference and Workshop on Emerging Trends in Technology 2014
%@ 0975-8887
%V ICWET2014
%N 2
%P 25-29
%D 2013
%I International Journal of Computer Applications
Abstract

Low-power design is becoming a crucial design objective for the chip design engineer due to the growing demand on portable application and the increasing difficulties in cooling and heat removal. In the integrated circuits power consumption is one of the challenges like area and speed . In this paper a novel technique is proposed to design an error detector for the lower power consumption. Here the work has done by using two low power flip flops (1)have considered SVL5T TSPC FF method and(2) low power DFF . In the proposed system reduction of power is about 50 % - 70%. Some of the low power flip flop is also used in multimedia and phase detector application.

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Index Terms

Computer Science
Information Sciences

Keywords

Flip Flop Low Power Logic Tspc Double Edge Triggering Svl Error Detector.