The week's pick
Reseach Article
Analysis of GAA Tunnel FET using MATLAB
| International Conference on Emerging Trends in Technology and Applied Sciences |
| Foundation of Computer Science USA |
| ICETTAS2015 - Number 1 |
| September 2015 |
| Authors: Praveen C S, Ajith Ravindran, Arathy Varghese |
Praveen C S, Ajith Ravindran, Arathy Varghese . Analysis of GAA Tunnel FET using MATLAB. International Conference on Emerging Trends in Technology and Applied Sciences. ICETTAS2015, 1 (September 2015), 30-35.
Abstract
In order to improve the energy efficiency of next generation digital systems, transistors with Subthreshold Slope < 45 mV/decade of drain current are needed. Tunnel Field Effect Transistor (TFET) s are attractive new devices for low power applications by its virtues of reduced short channel effects, low off current and their potential for a small subthreshold swing. TFETs ON current (ION) is usually very low. One solution is a double gate instead of a single gate structure, which will provide ION improvement. A gate all around (GAA) structure is preferred for further ION improvement without sacrificing OFF current (IOFF). In order to obtain high ION and low IOFF, a GAA TFET is modeled with a virtue of meeting the low power and high performance specifications of International Technology Roadmap of Semiconductors (ITRS) projected to year 2020, at a reduced drain voltage(VDD) = 0. 5 V.
References
- Q. Zhang, W. Zhao, and A. Seabaugh, "Low-subthreshold-swing tunnel transistors," IEEE Electron Device Letters, vol. 27, p. 297, 2006.
- S. O. Koswatta, M. S. Lundstrom, and D. E. Nikonov, "Performance Comparison Between p-i-n Tunneling Transistors and Conventional MOSFETs," IEEE Transactions on Electron Devices, vol. 56, pp. 456-465, 2009.
- Padilla, C. W. Yeung, C. Shin, C. Hu, and T. Liu "Feedback FET: A Novel Transistor Exhibiting Steep Switching Behavior at Low Bias Voltages" IEDM Tech. Dig. , pp. 1, 2008.
- K. Gopalakrishnan, P. B. Griffin, and J. D. Plummer, "Impact Ionization MOS (I-MOS) – Part I: Device and. Simulation,", IEEE Trans. Electron Dev. , Vol 52, pp 69, 2005.
- L. Esaki, "New Phenomenon in Narrow Germanium p - n Junctions", Physical Review, vol. 109, pp. 603-604, 1958.
- S. Banerjee, W. Richardson, J. Coleman and A. Chatterjee, "A new three-terminal tunnel device," IEEE Electron Device Letters, vol. 8, pp. 347-349, 1987.
- W. M. Reddick and G. A. Amaratunga, "Silicon surface tunnel transistor," Applied Physics Letters, vol. 67, no. 4, pp. 494-496, July 1995.
- S. M. Sze and K. K. Ng, Physics of Semiconductor Device, 3rd Edition, John Wiley & Sons, Inc. , pp. 422-425, 2007.
- Alan Seabaugh, The Tunneling Transistor, IEEE Spectrum, 30 Sep 2013.
- J. Knoch, S. Mantl, and J. Appenzeller, "Impact of the dimensionality on the performance of tunneling FETs: Bulk versus one-dimensional devices," Solid-State Electronics, vol. 51, pp. 572-578, 2007.
- B. G Streetman and S. Banerjee, Solid State Electronic Devices, 5th edn, New Jersey: Prentice Hall, Inc. , 2000.
- Verhulst, B. Sorée, D. Leonelli, W. Vandenberghe, and G. Groeseneken, "Modeling the singlegate, double-gate, and gate-all-around tunnel field-effect transistor," J. Appl. Phys. , vol. 107, pp. 024518-1-8, 2010.
- M. T. Bjoerk, O. Hayden, H. Schmid, H. Riel, and W. Riess, "Vertical surround-gated silicon nanowire impact ionization field-effect transistors" Appl. Phys. Lett. , Vol 90, pp 142110, 2007.
- N Singh, A Agarwal, L . K Bera, T. Y. Liow, R. Yang, S. C. Rustagi, C. H. Tung, R. Kumar, G. Q. Lo N. Balasubramanian and D. L. Kwong, " High performance fully depleted silicon nanowire (diameter < 5nm) gate all around CMOS devices", IEEE Electron Device Lett. , vol. 27, no. 5, pp. 383-386, May 2006.
- T. S. Arun Samuel, N . B. Balamurugan, T. Niranjana and B. Samyuktha, " Analytical Surface Potential Model with TCAD Simulation Verification for Evaluation of Surrounding Gate TFET", J Electr Eng Technol. , Vol. 9, No. 2: 655-661, 2009.
Index Terms
Keywords