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Reseach Article

High Speed 32-bit Vedic Multiplier for DSP Applications

by Arunkumar P. Chavan, Rahul Verma, Nishanth S. Bhat
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 135 - Number 7
Year of Publication: 2016
Authors: Arunkumar P. Chavan, Rahul Verma, Nishanth S. Bhat
10.5120/ijca2016908478

Arunkumar P. Chavan, Rahul Verma, Nishanth S. Bhat . High Speed 32-bit Vedic Multiplier for DSP Applications. International Journal of Computer Applications. 135, 7 ( February 2016), 35-38. DOI=10.5120/ijca2016908478

@article{ 10.5120/ijca2016908478,
author = { Arunkumar P. Chavan, Rahul Verma, Nishanth S. Bhat },
title = { High Speed 32-bit Vedic Multiplier for DSP Applications },
journal = { International Journal of Computer Applications },
issue_date = { February 2016 },
volume = { 135 },
number = { 7 },
month = { February },
year = { 2016 },
issn = { 0975-8887 },
pages = { 35-38 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume135/number7/24065-2016908478/ },
doi = { 10.5120/ijca2016908478 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T23:35:11.223052+05:30
%A Arunkumar P. Chavan
%A Rahul Verma
%A Nishanth S. Bhat
%T High Speed 32-bit Vedic Multiplier for DSP Applications
%J International Journal of Computer Applications
%@ 0975-8887
%V 135
%N 7
%P 35-38
%D 2016
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Digital signal processing typically requires large number of mathematical operations to be performed repeatedly on the samples of data with less delay and power consumption. Multiplication is the fundamental arithmetic operation and determines the overall execution time of the processor. In this paper two high speed 32-bit Vedic multipliers are designed based on Urdhva-Triyakhbhyam sutra. Addition of partial products of proposed multipliers is done using Kogge stone adder and ripple carry adder respectively. Proposed multiplier-1 and proposed multiplier-2 were compared with the one with the highest speed and a reduction of 77% and 65.37% is achieved respectively. The coding is done using Verilog HDL and synthesized using cadence tool.

References
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Index Terms

Computer Science
Information Sciences

Keywords

Vedic Mathematics Urdhva Triyakhbhyam Kogge Stone Adder High Speed.