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Efficient VLSI Architecture for DIT and DIF Fast Fourier Transform using Real Valued Data
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 167 - Number 8 |
| Year of Publication: 2017 |
| Authors: Neeraj Kumar Pandey, Pankaj Soni |
10.5120/ijca2017914406
|
Neeraj Kumar Pandey, Pankaj Soni . Efficient VLSI Architecture for DIT and DIF Fast Fourier Transform using Real Valued Data. International Journal of Computer Applications. 167, 8 ( Jun 2017), 29-32. DOI=10.5120/ijca2017914406
Abstract
With the upcoming of new innovation in the fields of VLSI and correspondence, there is additionally a perpetually developing interest for fast preparing and low territory outline. It is additionally a verifiable truth that the chip range and most propagation time unit shapes a necessary piece of processor outline. Because of this respect, rapid and low zone designs turn into the need of the day. A fast fourier transform (FFT) is any quick calculation for figuring the DFT. The advancement of FFT calculations tremendously affected computational parts of flag handling and connected science. The decimation in-time (DIT) fast Fourier transform (FFT) all the time has advantage over the decimation in-frequency (DIF) FFT for most genuine esteemed applications, similar to discourse/picture/video handling, biomedical flag preparing, and time-arrangement examination, and so forth., since it doesn't require any yield reordering.
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