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Design and Analysis of Low Power Level Shifter in IC Applications
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 141 - Number 11 |
| Year of Publication: 2016 |
| Authors: Meenu Singh, Priyanka Goyal, Ajeet Kumar Yadav |
10.5120/ijca2016909844
|
Meenu Singh, Priyanka Goyal, Ajeet Kumar Yadav . Design and Analysis of Low Power Level Shifter in IC Applications. International Journal of Computer Applications. 141, 11 ( May 2016), 6-10. DOI=10.5120/ijca2016909844
Abstract
In this paper, level Shifter circuit is analyzed which is efficient for converting low-voltage digital input signal into high-voltage digital output signal. The circuit has a diagnostic current generation device by using a logic error correction circuit that work by identifying the input and output logic level .When input signal changes, circuit produce low power operation only because it can dissipate power at the operating current. For the comparative analysis of this error correction Level Shifter different methodologies are used which named as biasing for the level Shifter. Result shows that the circuit converts a 0.4-V input signal to 3-V output signal. Simulation results are carried out by using 0.35μm CMOS technology. Power dissipation is 34nW for a 0.4V at 10 kHz input pulse.
References
- S. Rasool Hosseini1, Mehdi Saberi and Reza Lotfi, “An Energy-Efficient Level Shifter for Low-Power Applications” IEEE, 2015.
- K. M. Al-Ashmouny, S. Chang, and E. Yoon, “A 4μW/Ch. analog frontend module with moderate inversion and power-scalable sampling operation for 3-D neural microsystems,” IEEE Trans. Biomed. Circuits Syst., Vol.5, no.6, pp.403– 413, 2012.
- A. P. Chandrakasan, S. Sheng, and R. W. Brodersen, “Low-power CMOS digital design,” IEEE J. Solid-State Circuits, Vol. 27, no. 4, pp. 473–484, April 1992.
- A. Wang and A.P. Chandrakasan,” A 180mV sub-threshold FFT processor using a minimum energy design methodology,” IEEE J. Solid- State circuits, vol. 40, no. 1, pp. 310–319, 2005.
- K. Usami, M. Igarashi, F. Minami, T. Ishikawa, M.Kanazawa, M. Ichida, and K. Nogami, “ Automated low-power technique exploiting multiple supply voltages applied to a media processor,” IEEE J. Solid-State Circuits, Vol. 33, no. 3, pp. 463–472, March 1998.
- J. Chaitanya Varma, R. Ramana Reddy, D. Rama Devi “Sub Threshold Level Shifters and Level Shifter with LEC for LSI’s” (IJEAT) ISSN: 2249 – 8958, Volume-4 Issue-2, December 2014
- Yuji Osaki, Masahiro Numa and Tetsuya Hirose, “A Low-Power Level Shifter with Logic Error Correction for Extremely Low Voltage Digital CMOS LSIs” IEEE Journal of Solid-State Circuits, Vol. 47, no. 7, July 2012.
- Sung- Mo (Steve) Kang, Yusuf Leblebici, “Cmos Digital Integrated Circuits Analysis and Design” McGraws-Hill, 2003.
- Amrita Oza, Poonam Kadam, “Techniques for Sub-threshold Leakage Reduction in Low Power CMOS Circuit Designs” International Journal of Computer Applications (0975 – 8887) Vol. 97, no.15, July 2014.
- Y. Kim, D. Sylvester, and D. Belau, “LC: Limited contention level converter for robust wide-range voltage conversion,” in Dig. Symp. VLSI Circuits, 2011, pp. 188–189.
- Y. Moghe, T. Lehmann, and T. Piessens, “Nanosecond delay floating high voltage level shifters in a 0.35 m HV-CMOS technology,” IEEE J. Solid-State Circuits, Vol. 46, pp. 485–497, 2011.
- H. Shao and C.-Y. Tsui, “A robust, input voltage adaptive and low energy consumption level converter for sub-threshold logic,” in Proc. ESSCIRC, 2007, pp. 312–315
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