International Journal of Computer Applications |
Foundation of Computer Science (FCS), NY, USA |
Volume 130 - Number 8 |
Year of Publication: 2015 |
Authors: Naman Sharma, Rajat Sachdeva, Rajat Yadav, Upanshu Saraswat |
10.5120/ijca2015907075 |
Naman Sharma, Rajat Sachdeva, Rajat Yadav, Upanshu Saraswat . Implementation of a Fast and Power Efficient Carry Select Adder using Reversible Gates. International Journal of Computer Applications. 130, 8 ( November 2015), 28-31. DOI=10.5120/ijca2015907075
All reversible circuits have an intrinsic advantage over traditional irreversible circuits, because the reduce power consumption. Due to this, reversible circuits have been a source of constant excitement and great enthusiasm in the scientific community. Reversible logic is highly useful in nanotechnology, low power design and quantum computing. This paper proposes a design for a faster adder using reversible gates.