The week's pick
Random Articles
Reseach Article
Full adder Design using Hybrid Technology
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 130 - Number 7 |
| Year of Publication: 2015 |
| Authors: Ankita Gupta, Rajeev Thakur |
10.5120/ijca2015907029
|
Ankita Gupta, Rajeev Thakur . Full adder Design using Hybrid Technology. International Journal of Computer Applications. 130, 7 ( November 2015), 25-27. DOI=10.5120/ijca2015907029
Abstract
Full Adder is a fundamental element that is used in all the processor for not only in ALU but in various part of the chipset. The work proposes a Hybrid design methodology to contribute the requirements for the designing of full adder with reduced delay. The Analysis of the designed full adder is done at 270C and 700C temperature range in CMOS 120 nm, 90 nm, and 50 nm technologies using Microwind tool. The result shows the comparison between different CMOS technologies in terms of delay and power dissipation. A comparison is also done in terms of delay of the designed adder with previously known adder cells, which shows the advantage of the proposed design.
References
- John P. Uyemura, “Introduction to VLSI circuits and systems,” Wiley John & Sons, Inc, 2002.
- N. Weste, D. Harris, “CMOS VLSI Design,” Pearson Wesley, 2005.
- Sung-Mo Kang, Y. Leblebici, “CMOS Digital Integrated Circuits:Analysis and Design,” Tata McGraw Hill, 2003.
- SubodhWairya, GarimaSingh,Vishant, R. K.Nagaria, S. Tiwari Design Analysis of XOR (4T) based Low Voltage CMOS Full Adder Circuit INSTITUTE OF TECHNOLOGY, NIRMA UNIVERSITY, AHMEDABAD – 382 481, 08-10 DECEMBER, 2011.
- Hung Tien Bui, Yuke Wang and Yingtao Jiang, “Design and Analysis of Low-Power 10-Transistor Full Adders Using Novel XOR-XNOR Gates,” IEEE Transactions on Circuits & Systems II: Analog and Digital Signal Processing, vol. 49, no. 1, pp. 25-30, Jan. 2002.
- SumeerGoel, Ashok Kumar, Magdy A. Bayouni, “Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style,” IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 14, no. 12, pp. 1309-1321, Dec. 2006.
- J. Wang, S. Fang, W. Feng, New Efficient Designs for XOR and XNOR functions on the Transistor Level. IEEE Journal of Solid State Circuits,Vol. 29, No. 7, 1994, pp. 780-786
- R. Zimmermann, W. Fichtner, “Low-power logic styles CMOS versus pass-transistor logic,” IEEE J. Solid-StateCircuits, Vol. 32, pp. 1079–1090, July 1997
Index Terms
Keywords