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Reseach Article

Ant System for Routing in FPGA

by Pawan Kumar Dahiya, J.S. Saini, Shakti Kumar
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 130 - Number 15
Year of Publication: 2015
Authors: Pawan Kumar Dahiya, J.S. Saini, Shakti Kumar
10.5120/ijca2015907169

Pawan Kumar Dahiya, J.S. Saini, Shakti Kumar . Ant System for Routing in FPGA. International Journal of Computer Applications. 130, 15 ( November 2015), 1-6. DOI=10.5120/ijca2015907169

@article{ 10.5120/ijca2015907169,
author = { Pawan Kumar Dahiya, J.S. Saini, Shakti Kumar },
title = { Ant System for Routing in FPGA },
journal = { International Journal of Computer Applications },
issue_date = { November 2015 },
volume = { 130 },
number = { 15 },
month = { November },
year = { 2015 },
issn = { 0975-8887 },
pages = { 1-6 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume130/number15/23282-2015907169/ },
doi = { 10.5120/ijca2015907169 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T23:25:37.047759+05:30
%A Pawan Kumar Dahiya
%A J.S. Saini
%A Shakti Kumar
%T Ant System for Routing in FPGA
%J International Journal of Computer Applications
%@ 0975-8887
%V 130
%N 15
%P 1-6
%D 2015
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Routing of arbitrary placed blocks has been a long prevailing objective in any circuit in VLSI. In FPGA, the routing problem becomes more complex due to its fixed routing resources. An efficient routing algorithm tries to reduce the lengths of critical-path nets and also the congestion in the channel to improve the performance of the circuit. This paper presents an Ant System based approach, based on the intelligent behavior of ants, for the routing problem in FPGA. It is observed that the results after some iterations, converge towards the optimal solution at a better rate than other comparable techniques.

References
  1. K. Roy-Neogi and C. Sechen, “Multiple FPGA Partitioning with Performance Optimization,” Proceedings of the 3rd International ACM Symposium on Field-Programmable Gate Arrays, pp. 1-7, 1995.
  2. Pinaki Mazumdar and E.M. Rudnik, Genetic Algorithm for VLSI Design, Layout and Test Automation. Delhi: Pearson Education, 2003.
  3. P. Thomson and J.F. Miller, “Optimisation Techniques based on the use of Genetic Algorithms (GAS) for Logic Implementation on FPGAs,” The Institution of Electrical Engineers, pp. 411-414, 1994.
  4. G.K. Venayagamoorthy and V.G. Gudise, “Swarm Intelligence for Digital Circuits Implementation on Field Programmable Gate Arrays Platforms,” Proceedings of the NASA/DoD Conference on Evolvable Hardware (EH’04), pp. 1-4, 2004.
  5. Yee Leung, Guo Li, and Zong-Ben Xu, “A Genetic Algorithm for the Multiple Destination Routing Problems,” IEEE Transactions on Evolutionary Computation, Vol. 2, No. 4, pp. 150-161, 1998.
  6. M. Nakao and K. Izumi, “Circuit Designs and Fabrication of Swarm-Intelligence LSIs based on Modeling Foraging Behaviors of Ants,” The 47th IEEE International Midwest Symposium on Circuits and Systems, IEEE (0-7803-8346-X/04), pp. 97-100, 2004.
  7. Shakti, Kumar, J.S. Saini and Pawan Dahiya, “GAs for Routing in VLSI,” Proceedings of International Conference on Intelligent System and Networks, ISTK, Jagadhri, pp. 20-25, 2008.
  8. D. G. Prado and M. Ciesielski, “A Tutorial on FPGA Routing,” Dept. of Electrical and Computer Engg., University of Massachussets, pp.1-16.
  9. Russell G. Tessier , “Fast Place and Route Approaches for FPGAs,” Ph.D. thesis, Massachussets Institue of Technology, 1999.
  10. V.K. Jayaraman et.al., “Ant colony framework for optimal design and scheduling of batch plants” Computers and Chemical Engineering-24, pp. 1901-1912, 2000.
  11. J. E. Bell and P. R. McMullen, “Ant colony optimization techniques for the vehicle routing problem,” Advanced Engineering Informatics-18, pp. 41–48, 2004.
  12. K. M. Sim and W. H. Sun, “Ant colony optimization for routing and load-balancing: survey and new directions,” IEEE Transactions on Systems, Man, And Cybernetics—Part A: Systems and Humans, Vol. 33, No. 5, pp. 560-572, 2003.
  13. Marco Dorigo et.al., “Ant system: optimization by a colony of cooperating agents” IEEE Transactions on Systems, Man, And Cybernetics-Part B: Cybernetics, Vol. 26, No. 1, pp. 29-31, 1996.
  14. Marco Dorigo et.al., “Ant colony system: A cooperative learning approach to the traveling salesman problem,” IEEE Transactions on Evolutionary Computation, I (1), pp. 53-66, 1997.
  15. Marco Dorigo and Thomas Stutzle, Ant Colony Optimization. New Delhi: Prentice-Hall of India, 2005.
  16. Pawan Dahiya, J. S. Saini, and Shakti Kumar, “PSO for Routing Problem in VLSI,” International Conference on Intelligent Systems & Networks (ISN-2008), 2008.
  17. Pawan Dahiya, J. S. Saini, and Shakti Kumar, “Evolutionary Trends in VLSI Design,” Proc. of International Conference on Intelligent Systems & Networks (IISN-2007), 2007.
  18. Pawan Kumar Dahiya, “Recent Trends in Evolutionary Computation,” Ph.D. dissertation, ECE Dept., M. D. Univ., Rohtak, Haryana, India, 2011.
  19. Vineet Chaudhary, Parveen Kumar Yadav, and Pawan Kumar Dahiya, “Evaluation of cost optimization for travelling salesman problem (TSP) by comparing various ant colony optimization (ACO) algorithms,” International Journal of Computational Engineering & Management, Vol. 15, No. 5, pp. 38-44, 2012.
  20. Daniel Gomez-Prado Maciej Ciesielski, “A tutorial on FPGArouting,”Availableat:http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.84.9313&rep=rep1&type=pdf.
  21. John E. Bella, Patrick R. McMullen, “Ant colony optimization techniques for the vehicle routing problem,” Advanced Engineering Informatics 18, pp. 41–48,2004.
Index Terms

Computer Science
Information Sciences

Keywords

Field Programmable Gate Array (FPGA) Application Specific Integrated Circuits (ASIC) Routing Ant Colony Optimization (ACO).