The week's pick
Reseach Article
Implementation of on Chip Data Bus Using Pre Emphasis Signaling
Published on February 2012 by
Pallavi Dedge,
S.C. Badwaik
| Optimization and On-chip Communication |
| Foundation of Computer Science USA |
| OOC - Number 1 |
| February 2012 |
| Authors: Pallavi Dedge, S.C. Badwaik |
| 19464ea3-5770-4ee2-a4b6-9e7da3e9b57d |
Pallavi Dedge, S.C. Badwaik . Implementation of on Chip Data Bus Using Pre Emphasis Signaling. Optimization and On-chip Communication. OOC, 1 (February 2012), 32-39.
@article{
author = {
Pallavi Dedge,
S.C. Badwaik
},
title = { Implementation of on Chip Data Bus Using Pre Emphasis Signaling },
journal = {
Optimization and On-chip Communication
},
issue_date = { February 2012 },
volume = { OOC },
number = { 1 },
month = { February },
year = { 2012 },
issn = 0975-8887,
pages = {
32-39
},
numpages = 8,
url = {
/specialissues/ooc/number1/5469-1007/
},
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Special Issue Article
%1 Optimization and On-chip Communication
%A Pallavi Dedge
%A S.C. Badwaik
%T Implementation of on Chip Data Bus Using Pre Emphasis Signaling
%J Optimization and On-chip Communication
%@ 0975-8887
%V OOC
%N 1
%P 32-39
%D 2012
%I International Journal of Computer Applications
Abstract
This work describes a differential current-mode bus architecture based on driver pre-emphasis for on-chip global interconnects that achieves high-data rates while reducing bus power dissipation and improving signal delay latency. The 16-b bus core fabricated in 0.25- ? m complementary metalâoxideâsemi- conductor (CMOS) technology attains an aggregate signaling data rate of 64 Gb/s over 5â10-mm-long lossy interconnects. With a supply of 2.5 V, 25.5â48.7-mW power dissipation
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Index Terms
Computer Science
Information Sciences
Keywords