CFP last date

Published on December 2011 by
Z. Guitouni,
R. Chotin-Avot,
M. Machhout,
H. Mehrez,
R. Tourki

Network Security and Cryptography |

Foundation of Computer Science USA |

NSC - Number 4 |

December 2011 |

Authors: Z. Guitouni, R. Chotin-Avot, M. Machhout, H. Mehrez, R. Tourki |

67a2dbea-cac0-4995-8190-b21ac728deea |

Z. Guitouni, R. Chotin-Avot, M. Machhout, H. Mehrez, R. Tourki . High Performances ASIC Based Elliptic Curve Cryptographic Processor over GF(2m). Network Security and Cryptography. NSC, 4 (December 2011), 1-10.

@article{

author = {
Z. Guitouni,
R. Chotin-Avot,
M. Machhout,
H. Mehrez,
R. Tourki
},

title = { High Performances ASIC Based Elliptic Curve Cryptographic Processor over GF(2m) },

journal = {
Network Security and Cryptography
},

issue_date = { December 2011 },

volume = { NSC },

number = { 4 },

month = { December },

year = { 2011 },

issn = 0975-8887,

pages = {
1-10
},

numpages = 10,

url = {
/specialissues/nsc/number4/4342-spe039t/
},

publisher = {Foundation of Computer Science (FCS), NY, USA},

address = {New York, USA}

}

%0 Special Issue Article

%1 Network Security and Cryptography

%A Z. Guitouni

%A R. Chotin-Avot

%A M. Machhout

%A H. Mehrez

%A R. Tourki

%T High Performances ASIC Based Elliptic Curve Cryptographic Processor over GF(2m)

%J Network Security and Cryptography

%@ 0975-8887

%V NSC

%N 4

%P 1-10

%D 2011

%I International Journal of Computer Applications

Elliptic Curve Cryptography (ECC) has gained increasing acceptance in the industry, the academic community and the cryptography applications. This interest is mainly due to the high level of security with relatively small keys provided by ECC. In this paper, a high-performance ASIC based ECC key generation processor is proposed. This processor supports generic elliptic curves over GF(2m) with sizes (m) ranging from 113 to 256 bits. The proposed processor is based on programmable cellular automata. For real time implementation, the processor was simulated using active-HDL and synthesized using Synopsys Design Compiler. Further, the processor is implemented by an ASIC CMOS 120 nm technology. The results on the layouted processor over GF(2256) show a high performance, conﬁrming the efficiency of the processor.

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