This paper proposes the Application Specific Integrated Circuit (ASIC) implementation of Advanced Encryption Standard (AES) cryptographic algorithm with reconfigurable 128-bit, 192-bit, 256-bit keys. The proposed implementation has compact 32-bit I/O for both data and key transfer. By using on the fly key generation for encryption process along with efficient implementation of MixColumn and InverseMixColumn operations using finite field GF(22) for our 32-bit AES crypto system gives a maximum of 80.1% improvement in operating frequency when compared to the recent implementations. The maximum operating frequency of our proposed pipelined implementation is 333 MHz with high throughput of around 10.656 Gbps in 180 nm standard cell CMOS technology.

1. William Stallings, Cryptography and Network Security, Pearson Education, 2009.
2. National Institute of Standards and Technology (US), Advanced Encryption Standard, http://csrc.nist.gov/publication/drafts/dfips-AES.pdf.
3. B. Schnieir, Applied Cryptography, Wiley, New York, 1996.
4. P. Chodowiec and K. Gaj, “Very compact FPGA implementation of the AES algorithm,” Proceedings of Cryptographic Hardware and Embedded Systems (CHES), pp. 319-333, 2003.
5. Gael Rouvroy, Francois-Xavier Standaert and Jean-Jacques Quisquater, “Compact and efficient encryption / decryption module for FPGA implementation of the AES Rijndael very well suited for small embedded applications,” Proceedings of the International Conference on Information Technology : Coding and Computing (ITCC'04), 2004.
6. Chih-Pin Su, Tsung-Fu Lin, Chih-Tsiun Huang and Cheng-Wen Wu, “A high-throughput low cost aes processor,” IEEE Communications Magazine, vol. 41, no. 12, pp. 86-91, 2003.
7. Ingrid Verbauwhede, Patrick Schaumont, and Henry Kuo, “Design and performance testing of a 2.29 Gb/s Rijndael processor,” IEEE Journal of solid-state circuits, vol. 38, no. 3, 2003.
8. F. Haghighizadeh, H. Attarzadeh and M. Sharifkhani, “A Compact 8-bit AES Crypto-Processor,” Second International Conference on Computer and Network Technology (ICCNT'10), 2010.
9. N. Sklavos and O. Koufopavlou, “Architectures and VLSI implementations of the AES-Proposal Rijndael,” IEEE Transactions on computers, vol. 51 no. 12, pp. 1454-1459, 2002.
10. X. Zhang and K. Parhi, “High speed VLSI Architectures for the AES algorithm,” IEEE transactions on VLSI systems, vol. 12, no. 9, 2004.
11. S.M. Yoo, D. Kotturi, D.W. Pan and J. Blizzard, “An AES crypto chip using a high-speed parallel pipelined architecture,” Journal of Microprocessors and Microsystems, pp. 317-326, 2005.
12. S. Mangard, M. Aigner, and S. Dominikus, “A highly regular and scal-able AES hardware architecture,” IEEE Trans. Comput. , vol. 52, no. 4,pp. 483–491, Apr. 2003
13. A. Satoh, S. Morioka, K. Takano, and S. Munetoh, “A compact Rijn-dael hardware architecture with S-box optimization,” in ASIA CRYPT 2001 .Berlin, Germany: Springer-Verlag, 2001, vol. 2248, LNCS, pp. 239–254.
14. C.-P. Su, T.-F. Lin, C.-T. Huang, and C.-W. Wu, “A high-throughput low-cost AES processor,” IEEE Commun. Mag. ,vol. 41, no. 12, pp. 86–91, Dec. 2003.
15. C.-H. Yen, T.-Y. Pai, and B.-F. Wu, “The implementations of the re-configurable Rijndael algorithm with throughput of 4.9 Gbps,” in Proc.16th VLSI Des./CAD Symp. , Hualien, Taiwan, Aug. 2005.
16. Mao –Yin Wang, Chih –Pin Su, Chia- Lung Horng, Cheng –Wen Wu and Chih- Tsun Huang, “ Single- and Multi-core Configurable AEs Architectures for Flexible Security,” IEEE Transactions on Very Large Scale Integration(VLSI) Systems, Vol. 18,No.4, April 2010.

Keywords - AES Cryptography Galois Field GF(28) On the fly key generation Throughput