The demand for increasing speed and low power dissipation triggers numerous research efforts with the increasing demand of wireless portable communication systems in underground mines driven by batteries. Presence of highly flammable gases in underground mines prohibits the use of higher power dissipating electronic systems. Low power wireless portable communication devices can safeguard the life of miners in case of disaster. The demand for increased battery life of portable devices has forced researchers to seek out new integrated circuit techniques to reduce the power dissipation without comprise in performance of the portable electronic system. Power consumption by the electronic system determines the battery life of the device. As a result, tremendous effort has been devoted to achieve lower power dissipation without affecting performance of portable communication devices. Therefore, reduction of power dissipation without sacrifice in performance is vital for wireless portable communication devices for improving the safety standards and productivity in underground mines. Multi threshold circuit technique can be used to design a low power high performance integrated circuit for wireless portable communication devices used in underground mines.

1. L.K.Bandyopadhyay, S.K.Chaulya, M.K.Dutta, A.Narayan and Manish Kumar, “Development of an environmental monitoring system for underground coal mines”, in proceedings of International Conference on Coal Science and Technology, Global Coal, pp. 49-55, 2005.
2. www.easterncoal.gov.in
3. Fred Pollack, “32nd IEEE Annual International Symposium on Microarchitecture”, 1999. www.huron.cs.ucdavis.edu/Micro32/homepage.html
4. P. Gelsinger, “Gigascale Integration for Teraops Performance: Challenges,Opportunities, and New Frontiers," in proceedings of the 41st Design Automation Conference, pp.15-17, 2004.
5. Manish Kumar, Md. A. Hussain and L.K.Singh, “Design of a Low Power High Speed ALU in 45nm Using GDI Technique and Its Performance Comparison”, Communications in Computer and Information Science, Volume 142, Part 3, pp. 458-463, 2011.
6. A. Chandrakasan and R. Brodersen, “Minimizing Power Consumption in Digital CMOS Circuits” , in proceedings of IEEE, vol. 83, no. 4, pp. 498-523, 1995.
7. A. Chatterjee, “An Investigation of the Impact of Technology Scaling on Power Wasted as Short-circuit Current in Low Voltage Static CMOS Circuits", in proceedings of the International Symposium on Low Power Electronics and Design,ISLPED, pp. 145-150,1996.
8. Sung Mo Kang and Yusuf Leblebici, “CMOS Digital Integrated Circuits-Analysis and Design”, Tata McGraw Hill, Third Edition, New Delhi, 2003.

Power dissipation Portable device Multi threshold circuit technique Leakage current Mean squared Error