International Conference on Electronics, Information and Communication Engineering |
Foundation of Computer Science USA |
ICEICE - Number 2 |
December 2011 |
Authors: Rajesh Adluri, G. Surender Babu, Philemon Daniel |
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Rajesh Adluri, G. Surender Babu, Philemon Daniel . FPGA Implementation of Multi-alphabet Arithmetic Coding Using Rotating Intervals. International Conference on Electronics, Information and Communication Engineering. ICEICE, 2 (December 2011), 10-14.
We present a modified AC scheme for multi-alphabet that offers both encryption and compression. The system utilises an arithmetic coder in which the overall length within the range [0, 1] allocated to each symbol is upheld, but the conventional assumption that the orientation of the symbols remains unchanged throughout the process is removed. The encryption and compression can be carried out simultaneously, by rotating intervals that are invoked by a rotation key without affecting the efficiency. The proposed methodology also facilitates a direction key to make the rotations in either direction.