The week's pick
Reseach Article
BER Analysis for Different Number of Inserted Flip-Flop and Latches
| International Conference on Electronics, Information and Communication Engineering |
| Foundation of Computer Science USA |
| ICEICE - Number 1 |
| December 2011 |
| Authors: Devendra Giri, Gagnesh Kumar |
| a8dd88ba-80a8-4a07-8c15-f0315f06cf90 |
Devendra Giri, Gagnesh Kumar . BER Analysis for Different Number of Inserted Flip-Flop and Latches. International Conference on Electronics, Information and Communication Engineering. ICEICE, 1 (December 2011), 34-37.
Abstract
In this paper a detailed analysis for how the number of flip-flops and latches inserted are effecting BER and repeater size with wire pipelining is performed. Since number of flip-flops, latches and repeater sizes cannot scaled down beyond a certain limit due to the solidity requirement, which is determined by maximum allowable bit error rate.
References
- Lou Scheffer, “Methodologies and Tools for Pipelined On-Chip Interconnect,” IEEE International Conference on Computer Design: VLSI in Computers and Processor, September 2002,pp.152-157.
- J. Xu, M. H. Chowdhury “Bit Error Rate Analysis for Flip-flop and Latch Based Interconnect Pipelining”, 13th IEEE International Conference on Electronics, Circuits and Systems(ICECS06), InPress.
- V. Nookala, S. S. Sapatnekar, “Designing optimized pipelined global interconnects: Algorithms and methodology impact,” IEEE International Symposium on Circuit and systems, May 2005, Vol.1, pp. 608-611.
- R. Lu, G. Zhong, K. Cheng, K. Chao, “Flip-Flop and Repeater Insertion for Early Interconnect Planning,” Design Automation and Test in Europe Conference and Exhibition, pp.690-695, March 2002.
- L. Zhang, Y. Hu, and C. C. P. Chen, “Wave-Pipelined On-Chip Global Interconnect”, Design Automation Conference, January 2005, Vol.1, pp. 46-51.
- V. Seth, M. Zhao, J. Hu, “Exploiting Level Sensitive Latches in Wire Pipelining,” International Conference on Computer Aided Design, November 2004, pp.283-290.
- B. Kong, S.-S. Kim, and Y.-H. Jun, “Conditional-capture flip-flop technique for statistical power reduction,” in IEEE Int. Solid-State Circuits Conf., Feb. 2000, pp. 290–291.
- J. Xu, M.H. Chowdhury “Latch Based Interconnect Pipelining For High Speed Integrated Circuits”, Sixth International Conference on Electro/Information Technology (EIT06). May 2006
- R. Lu, G. Zhong, K. Cheng, K. Chao, Flip-Flop and repeater Insertion for Early Interconnect Planning, “Design Automation and test in EuropeConference and Exhibition, March 2002,pp.690-695.”
- J. Xu, M.H. Chowdhury Latch Based Interconnect Pipelining For High Speed Integrated Circuits , “Sixth International Conference on Electro/Information Technology (EIT06). May 2006”.
Index Terms
Keywords