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New Architecture of Parallel FIR Filter using Fast FIR Algorithm

Published on November 2012 by B. Divya, A. Azhagu Jaisudhan Pazhani
journal_cover_thumbnail

International Conference on Electronics, Communication and Information systems
Foundation of Computer Science USA
ICECI - Number 3
November 2012
Authors: B. Divya, A. Azhagu Jaisudhan Pazhani
cc16d4c2-857e-405d-9753-bbeb83b74f80

B. Divya, A. Azhagu Jaisudhan Pazhani . New Architecture of Parallel FIR Filter using Fast FIR Algorithm. International Conference on Electronics, Communication and Information systems. ICECI, 3 (November 2012), 22-27.

@article{
author = { B. Divya, A. Azhagu Jaisudhan Pazhani },
title = { New Architecture of Parallel FIR Filter using Fast FIR Algorithm },
journal = { International Conference on Electronics, Communication and Information systems },
issue_date = { November 2012 },
volume = { ICECI },
number = { 3 },
month = { November },
year = { 2012 },
issn = 0975-8887,
pages = { 22-27 },
numpages = 6,
url = { /specialissues/iceci/number3/9477-1026/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Special Issue Article
%1 International Conference on Electronics, Communication and Information systems
%A B. Divya
%A A. Azhagu Jaisudhan Pazhani
%T New Architecture of Parallel FIR Filter using Fast FIR Algorithm
%J International Conference on Electronics, Communication and Information systems
%@ 0975-8887
%V ICECI
%N 3
%P 22-27
%D 2012
%I International Journal of Computer Applications
Abstract

A New parallel FIR Filter structures is proposed based on fast-finite impulse response algorithms, which are beneficial to symmetric coefficients. Parallel (or block) FIR digital filter can be used either for high speed or low- power (with reduced supply voltage) applications. The New parallel FIR structures exploit the inherent nature of symmetric coefficients reducing half the number of multipliers in sub-filter section at the expense of additional adders in pre-processing and post processing blocks. The overhead from additional adders does not increase along the length of the FIR Filter; moreover adders weigh less than multipliers in terms of silicon area. Overall the new parallel FIR structures can lead to significant hardware savings for symmetric convolutions from existing FFA parallel FIR filter especially when the length of the filter is large. The new parallel FIR structures consisting of advantageous polyphase decomposition dealing with symmetric convolutions comparatively better than the existing FFA structures.

References
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Index Terms

Computer Science
Information Sciences

Keywords

Digital Signal Processing(dsp) fast Finite Impulse Response(fir)algorithm(ffas) Parallel Fir Symmetric Convolution very Large Scale Integration(vlsi)