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Reduction of Hardware Complexity and Truncation Error by using Fixed Width Baugh Wooley Multiplier

Published on November 2012 by P. Arun Pandian, T. Vijaya Bharathi
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International Conference on Electronics, Communication and Information systems
Foundation of Computer Science USA
ICECI - Number 3
November 2012
Authors: P. Arun Pandian, T. Vijaya Bharathi
0f065ed3-1af6-4f74-a437-e3b852b94ac6

P. Arun Pandian, T. Vijaya Bharathi . Reduction of Hardware Complexity and Truncation Error by using Fixed Width Baugh Wooley Multiplier. International Conference on Electronics, Communication and Information systems. ICECI, 3 (November 2012), 10-13.

@article{
author = { P. Arun Pandian, T. Vijaya Bharathi },
title = { Reduction of Hardware Complexity and Truncation Error by using Fixed Width Baugh Wooley Multiplier },
journal = { International Conference on Electronics, Communication and Information systems },
issue_date = { November 2012 },
volume = { ICECI },
number = { 3 },
month = { November },
year = { 2012 },
issn = 0975-8887,
pages = { 10-13 },
numpages = 4,
url = { /specialissues/iceci/number3/9474-1022/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Special Issue Article
%1 International Conference on Electronics, Communication and Information systems
%A P. Arun Pandian
%A T. Vijaya Bharathi
%T Reduction of Hardware Complexity and Truncation Error by using Fixed Width Baugh Wooley Multiplier
%J International Conference on Electronics, Communication and Information systems
%@ 0975-8887
%V ICECI
%N 3
%P 10-13
%D 2012
%I International Journal of Computer Applications
Abstract

The fixed-width multiplier is attractive to many multimedia and digital signal processing systems which are desirable to maintain a fixed format and allow a little accuracy loss to output data. In this paper, we propose a new error compensation circuit in Baugh-Wooley multiplier by using the dual group minor input correction (MIC) vector to lower input correction vector compensation error. By constructing the error compensation circuit mainly from the "outer" partial products, the hardware complexity only increases slightly as the multiplier input bits increase. In the proposed 16 *16 bits fixed-width multiplier, the truncation error can be lowered by compared with the direct-truncated multiplier and the transistor count can be reduced by compared with the full-length multiplier.

References
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Index Terms

Computer Science
Information Sciences

Keywords

Baugh Wooley Multiplier Ao Block Modified Half Adder Vhdl Simulation