International Conference on Electronics, Communication and Information systems |
Foundation of Computer Science USA |
ICECI - Number 3 |
November 2012 |
Authors: M. Petchiammal, G. Ramyadevi |
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M. Petchiammal, G. Ramyadevi . Design of 16-bit Countermeasure Circuit with AES Algorithm for AES Engine. International Conference on Electronics, Communication and Information systems. ICECI, 3 (November 2012), 1-5.
The DPA attack can efficiently disclose the secret key of an AES Engine easily. To increase DPA Resistant of the AES engine by XORing the generated 16 bit from Pseudo Random Number Generator with the cipher text from the AES Engine. The cipher text is created by AES algorithm which is very Efficient Algorithm for data Securing. The 16 Bit Sequence Generator Circuit also provide Reduction in Area occupied by the Countermeasure circuit and Delay of propagation time by using pipelining process. The Speed of the DPA Countermeasure circuit also increased without degradation in throughput.