A low power pulse triggered ?ip?op (P-FF) design is done by the pulse generation control logic, an AND function, is removed from the critical path to facilitate a faster discharge operation. A simple two-transistor AND gate design is used to reduce the circuit complexity. A conditional pulse enhancement technique is devised to speed up the discharge along the critical path only when needed. As a result, transistor sizes in delay inverter and pulse generation circuit can be reduced for power saving. Various post layout simulation results based on UMC CMOS 90-nm technology reveal that the enhanced pulse triggered FF design features the best power-delay-product performance in seven FF designs under comparison. Its maximum power saving against rival designs is up to 38. 4%. Compared with the conventional transmission gate based flipflop design. The average leakage power consumption is also reduced by a factor of 3. 52.

1. P. Zhao, J. McNeely, W. Kaung, N. Wang, and Z. Wang, 2011. "Design of sequential elements for low power clocking system," IEEE Trans. Very Large Scale Integr. (VLSI) System.
2. H. Mahmoodi, V. Tirumalashetty, M. Cooke, and K. Roy, 2009. "Ultra low power clocking scheme using energy recovery and clock gating," IEEE Trans. Very Large Scale Integrated. (VLSI) system.
3. C. K. Teh, M. Hamada, T. Fujita, H. Hara, N. Ikumi, and Y. Oowaki, 2006. "Conditional data mapping ?ip-?ops for low-power and high-performance systems," IEEE Trans. Very Large Scale Integr. (VLSI) Systems.
4. Y. -H. Shu, S. Tenqchen, M. -C. Sun, and W. -S. Feng, 2006 "XNOR-based double-edge-triggered ?ip-?op for two-phase pipelines," IEEE Trans. Circuits Systems. II, Exp. Briefs.
5. A. G. M. Strollo, D. De Caro, E. Napoli, and N. Petra, 2005. "A novel high speed sense-ampli?er-based ?ip-?op," IEEE Trans. Very Large Scale Integrated. (VLSI) System.
6. S. H. Rasouli, A. Khademzadeh, A. Afzali-Kusha, and M. Nourani, 2005 "Low power single- and double-edge-triggered ?ip-?ops for high speed applications," Proc. Inst. Electr. Eng. Circuits Devices System.
7. P. Zhao, T. Darwish, and M. Bayoumi, 2004 "High-performance and low power conditional discharge ?ip-?op," IEEE Trans. Very Large Scale Integr. (VLSI) System.
8. V. G. Oklobdzija, 2003 "Clocking and clocked storage elements in a multi-giga-hertz environment," IBM J. Res. Devel.
9. S. D. Naffziger, G. Colon-Bonet, T. Fischer, R. Riedlinger, T. J. Sullivan, and T. Grutkowski, 2002 "The implementation of the Itanium 2 microprocessor," IEEE J. Solid-State Circuits.
10. N. Nedovic, M. Aleksic, and V. G. Oklobdzija, 2002 "Conditional precharge techniques for power-ef?cient dual-edge clocking," in Proc. Int. Symp. Low-Power Electron. Design.
11. B. Kong, S. Kim, and Y. Jun, 2001 "Conditional-capture ?ip-?op for statistical power reduction," IEEE J. Solid-State Circuits.
12. J. Tschanz, S. Narendra, Z. Chen, S. Borkar, M. Sachdev, and V. De, 2001 "Comparative delay and energy of single edge-triggered and dual edge triggered pulsed ?ip-?ops for high-performance microprocessors,"
13. F. Klass, C. Amir, A. Das, K. Aingaran, C. Truong, R. Wang, A. Mehta, R. Heald, and G. Yee, 1999 "A new family of semi-dynamic and dynamic ?ip ?ops with embedded logic for high-performance processors," IEEE J. Solid-State Circuits.
14. H. Kawaguchi and T. Sakurai, 1998 "A reduced clock-swing ?ip-?op (RCSFF) for 63% power reduction," IEEE J. Solid-State Circuits.
15. H. Partovi, R. Burd, U. Salim, F. Weber, L. DiGregorio, and D. Draper, 1996 "Flow-through latch and edge-triggered ?ip-?op hybrid elements," in IEEE Tech.

Flip?op Low Power Pulse Triggered