The week's pick
Reseach Article
Design and Realization of FPGA based Off-Chip Trained MLP for Classical XOR Problem and Need of On-Chip Training
| International Conference on Electronics, Communication and Information systems |
| Foundation of Computer Science USA |
| ICECI - Number 2 |
| November 2012 |
| Authors: K. Packia Lakshmi, M. Subadra |
| 8889652d-b454-4b0d-b5cc-54f9c79c6563 |
K. Packia Lakshmi, M. Subadra . Design and Realization of FPGA based Off-Chip Trained MLP for Classical XOR Problem and Need of On-Chip Training. International Conference on Electronics, Communication and Information systems. ICECI, 2 (November 2012), 7-12.
Abstract
The main intension of this work is to present the importance of neural chip with learning capability. The designed sequentially trained MLP structure is used to solve the classical XOR problem and the structure is realized on FPGA device environment. By comparing the device utilization summary for the design in different families of Xilinx FPGA, the importance of platform selection for hardware implementation is presented. Finally the importance of on-chip learning is emphasized.
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