The week's pick
Reseach Article
Design of Low Complexity Encoder for Capacitively Coupled VLSI Interconnects
| Evolution in Networks and Computer Communications |
| Foundation of Computer Science USA |
| ENCC - Number 2 |
| None 2011 |
| Authors: Deepika Agarwal, G. Nagendra Babu, B. K. Kaushik, S. K. Manhas |
| 4a266afb-e10d-4976-acd9-609d0f5f3912 |
Deepika Agarwal, G. Nagendra Babu, B. K. Kaushik, S. K. Manhas . Design of Low Complexity Encoder for Capacitively Coupled VLSI Interconnects. Evolution in Networks and Computer Communications. ENCC, 2 (None 2011), 45-49.
Abstract
In current Deep Submicron (DSM) era, interconnects play important role in overall performance of the chip. The factors such as power dissipation and crosstalk through RC modeled interconnects substantially affect the entire working of the chip. Therefore, to enhance the performance, minimization or elimination of coupling between interconnects is essential. Bus-invert method is the best method which can simultaneously reduce coupling and power consumption of interconnects. The proposed method focuses on designing low complexity encoder for 4, 8 and 16 bit RC coupled lines. The encoder proposed occupies 37% lesser area than the most popular encoder. The power consumption of this encoder is 68% lesser and the overall delay is also reduced by 57% compared to the existing encoders for RC modeled interconnects.
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