The performance of VLSI/ULSI chip is becoming less predictable as device dimensions shrinks below the sub-100-nm scale. Process variation is considered to be a major concern in the design of circuits including interconnect pipelines in current deep submicron regime. Process variation results in uncertainties of circuit performances such as propagation delay. The reduced predictability can be attributed to poor control of the physical features of devices and interconnects during the manufacturing process. Variations in these quantities maps to variations in the electrical behavior of circuits. The channel width of MOSFET varies due to changes in drain/source thickness; substrate, polysilicon and implant impurity level; and surface charge. This paper provides a comprehensive analysis of the effect of channel width variation on the propagation delay through driver-interconnect-load (DIL) system. The impact of process induced driver width variations on propagation delay of the circuit is discussed for three different technologies i.e. 130nm, 70nm and 45nm. The comparison of results between these three technologies shows that as device size shrinks, the process variation issues becomes dominant during design cycle and subsequently increases the uncertainty of the delays.

1. Sai-Halasz, G. A. 1995. Performance trends in high-end processors. Proceedings of IEEE. vol. 83, no. 1, (Jan. 1995), 20 - 36.
2. Sylvester, D. and Wu, C. 2001. Analytical modeling and characterization of deep-submicrometer interconnect. Proceed. of IEEE. Vol. 89, no. 5 (May 2001), 634-664.
3. Kaushik, Brajesh Kumar, Sarkar, Sankar and Agarwal, R. P. 2008. Crosstalk Analysis for a CMOS-Gate-Driven Coupled Interconnects. IEEE Trans. on Computer Aided Design of Integrated Circuits and Systems. vol. 27, no. 6 (Jun. 2008), 1150-1154.
4. Orshansky, M., Milor, L., Chen,P., Keutzer, K., and Hu, C. 2000. Impact of systematic spatial intra-chip gate length variability on performance of high-speed digital circuits. In Proceedings of International Conference on Computer-Aided Design (ICCAD), 62–67.
5. Liu, Y., Nassif, S. R., Pileggi, L. T., and Strojwas, A. J. 2000. Impact of interconnect variations on the clock skew of a gigahertz microprocessor. in Proceedings of Design Automation Conference (DAC), 168–171.
6. Mehrotra, V., Sam, S., Boning, L. D., Chandrakasan, A., Vallishayee, R., and Nassif, S. 2000. A methodology for modeling the effects of systematic within-die interconnect and device variation on circuit performance. In Proceedings of Design Automation Conference (DAC), 172–175.
7. Malavasi, E., Zanella, S., Min, J., Uschersohn, C., Misheloff, M. and Guardiani, C. 2002. Impact analysis of process variability on clock skew. International Symposium on Quality Electronic Design (ISQED), 129–132.
8. Brawhear, R. B., Menezes, N., Oh, C., Pillage, L. T., and Mercer, M. R. 1994. Predicting circuit performance using circuit-level statistical timing analysis. in Proceedings of Design, Automation, and Test in Europe (DATE), 332–337.
9. Chang, H., and Sapatnekar, S. S. 2003. Statistical timing analysis considering spatial correlations using a single PERT-like traversal. in Proceedings of International Conference on Computer-Aided Design (ICCAD), 621–625.
10. Agarwal, A., Blaauw, D., and Zolotov, V. 2003. Statistical timing analysis for intra-die process variations with spatial correlations. In Proceedings of International Conference on Computer-Aided Design (ICCAD), 271–276.
11. Acar, E., Nassif, S. N., Ying, L., and Pileggi, L. T. 2001. Assessment of true worst case circuit performance under interconnect parameter variations. International Symposium on Quality Electronic Design (ISQED), 431–436.
12. Borkar, S., Kamik, T., Narendra, S., Tschanz, J., Keshavarzi, A., and De, V. 2003. Parameter variations and impact on circuits and microarchitecture. In Proceedings of Design Automation Conference (DAC), 338–342.
13. Gattiker, A., Nassif, S., Dinakar, R., and Long, C. 2001. Timing yield estimation from static timing analysis. In Proceedings of International Symposium on Quality Electronic Design (ISQED), 437–442.
14. Luong, G. M., and Walker, D. M. H. 1996. Test generation for global delay faults. In Proceedings of IEEE International Test Conference (ITC), 433–442.
15. Liou, J. J., Krstic, A., Wang, L. C. and Cheng, K. T. 2002. False path-aware statistical timing analysis and efficient path selection for delay testing and timing validation. In Proceedings of Design Automation Conference (DAC), 566–569.
16. Krstic, A., Wang, L. C., Cheng, K. T. and Liou, J. J. 2003. Diagnosis of delay defects using statistical timing models. IEEE VLSI Test Symposium (VTS), 339–344.
17. Lu, X., Li, Z., Qiu, W., Walker, D. M. H., and Shi, W. 2004. Longest path selection for delay test under process variation. In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), 99-103.
18. Fabbro, A. D., Franzini, B., Croce, L. and Guardiani, C. 1995. An assigned probability technique to derive realistic worst-case timing models of digital standard cells. In Proceedings of Design Automation Conference (DAC), 702–706.
19. Vrudhula, S., Wang, J. M., and Ghanta, P. 2006. Hermite Polynomial Based Interconnect Analysis in the Presence of Process Variations. IEEE Trans. on CAD of Integrated Circuits And Systems. Vol. 25, no. 10 (Oct. 2006), 2001-2011.
20. Verma, K. G., Kaushik, B. K., Singh, R. 2011. Deviation in Propagation Delay due to Process Induced Driver Width Variation. International Journal of Electronics and Communication Technology. Vol. 2, no. 1 (Mar. 2011).
21. Verma, K. G., Singh, Raghuvir, Kaushik, B. K. and Kumar, Brijesh. 2011. Propagation Delay Deviations due to Process Tempted Driver Width Variations. In Proceedings of IEEE Int. Conf. on International Conference on Networks and Computer Communications, 89-92.
22. Majumder, M. K., Kaushik, B. K. and Manhas, S. K. 2011. Performance Comparison between Single wall Carbon Nanotube Bundle and Multiwall Carbon Nanotube for Global Interconnects. In Proceedings of the IEEE International Conference on Networks and Computer Communications, 104-109.

Process variation parasitic propagation delay driver width load technology node