The week's pick
Reseach Article
Hardware Implementation of Mix Column Step in AES
| Communication and Networks |
| Foundation of Computer Science USA |
| COMNETCN - Number 1 |
| December 2011 |
| Authors: Pratap Kumar Dakua, Manoranjan Pradhan, Subba Rao Polamuri |
| 3798ecf7-12e9-44e2-acb7-fe28e2ac701e |
Pratap Kumar Dakua, Manoranjan Pradhan, Subba Rao Polamuri . Hardware Implementation of Mix Column Step in AES. Communication and Networks. COMNETCN, 1 (December 2011), 6-9.
Abstract
This document gives the hardware implementation of Mix Column step in AES encryption process. The AES encryption process consists of several transformation steps such as byte substitution, shift rows, mix column and addition of round key operation step. There are two aspects to perform mix column step in AES is presented. The total operation is coded with VERILOG, synthesized and simulated using Xilinx ISE 10.1.
References
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