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Design of User Define Instruction Set using APU

Published on March 2013 by Pratap Khuntia, Soumyashree Sethy
journal_cover_thumbnail

International Conference on Computing, Communication and Sensor Network
Foundation of Computer Science USA
CCSN2012 - Number 2
March 2013
Authors: Pratap Khuntia, Soumyashree Sethy
0b8a7140-bc9a-4ca5-b978-b76e71eb6671

Pratap Khuntia, Soumyashree Sethy . Design of User Define Instruction Set using APU. International Conference on Computing, Communication and Sensor Network. CCSN2012, 2 (March 2013), 19-23.

@article{
author = { Pratap Khuntia, Soumyashree Sethy },
title = { Design of User Define Instruction Set using APU },
journal = { International Conference on Computing, Communication and Sensor Network },
issue_date = { March 2013 },
volume = { CCSN2012 },
number = { 2 },
month = { March },
year = { 2013 },
issn = 0975-8887,
pages = { 19-23 },
numpages = 5,
url = { /specialissues/ccsn2012/number2/10855-1017/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Special Issue Article
%1 International Conference on Computing, Communication and Sensor Network
%A Pratap Khuntia
%A Soumyashree Sethy
%T Design of User Define Instruction Set using APU
%J International Conference on Computing, Communication and Sensor Network
%@ 0975-8887
%V CCSN2012
%N 2
%P 19-23
%D 2013
%I International Journal of Computer Applications
Abstract

This paper includes User Defined Instruction Decoding using the Auxiliary Processor Unit (APU) controller which allows the designer to extend the native PowerPC 405 instruction set with custom instructions that are executed by an FPGA Fabric Co-processor Module (FCM) which accelerate the system performance with the APU Controller, with an aim that Portions of certain software applications that are implemented in software can run faster by moving the implementation into hardware. In a Virtex™-4 FX FPGA, the embedded PowerPC™ 405 (PPC405) processor can run software and offload computations to hardware modules in the FPGA. In such a system, a coprocessor interface known as the Auxiliary Processor Unit (APU) is used to transfer data between the processor and the FPGA. Because certain computations can be done more efficiently in software, and others in hardware, an APU-enhanced system results in a faster overall solution for many digital signal processing (DSP) applications.

References
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  9. A. Ansari, P. Ryser, and D. Isaacs, "Accelerating System Performance with APU-Enhanced Processing", Xcell Journal, First Quarter2005.
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  11. "Accelerated System Performance with the APU Controller and Xtreme DSP Slices", xapp717 (v1. 1. 1) Sept. 29, 2005, @ www. xilinx. com.
Index Terms

Computer Science
Information Sciences

Keywords

User Define Instruction Apu Fcm Co-processor Embedded Powerpc