The week's pick
Reseach Article
Low Power Test Pattern Generator for System on Chip Architecture
| International Conference on Computing, Communication and Sensor Network |
| Foundation of Computer Science USA |
| CCSN2012 - Number 2 |
| March 2013 |
| Authors: Ajit Kumar Mohanty, Biswanath Pratap Sahu, Chandan Patnaik, S. S. Mahato |
| cfd2b1be-b870-4e1f-8a7e-3d76353f88aa |
Ajit Kumar Mohanty, Biswanath Pratap Sahu, Chandan Patnaik, S. S. Mahato . Low Power Test Pattern Generator for System on Chip Architecture. International Conference on Computing, Communication and Sensor Network. CCSN2012, 2 (March 2013), 11-15.
Abstract
Low Power test pattern generator using a linear feedback shift register (LFSR), called LP-TGP is presented to reduce the average and peak power of a circuit during test. The correlation between two test patterns generated by LP-TPG is more than between the random patterns. The goal of having intermediate patterns is to reduce the transitional activities of primary inputs which reduces the switching activities inside the circuit under test and hence power consumption. An experimental result shows that proposed method gives 30. 87% reduction in power during testing.
References
- Y. Zorian, "A Distributed BIST Control Scheme for ComplexVLSI Devices," Proc. 11th IEEE VLSI Test Symp. , Atlantic City, New Jersy, pp. 4-9, Apr. 1993. 4-9, Apr. 1993.
- Bo Ye and Tian-Wang Li , "A Novel BIST Scheme For Low Power Testing",3rd IEEE International Conference on Computer Science and Information Technology (ICCSIT) , 2010 ,Volume:1,Digital Object Identifier : 10. 1109/ICCSIT. 2010. 553904, Pages: 134-137, Publication Year: 2010.
- S. C. Lei, J. Guo, L. Cao, Z. Ye. Liu, and X. M. Wang, "SACSR: A Low Power BIST Method for Sequential Circuits," Academic journal of XI'AN jiaotong university (English Edition), vol. 20, no. 3, pp. 155-159, 2008.
- R. S. Katti, X. Y. Ruan, and H. Khattri, "Multiple-output low power linear feedback shift register design," IEEE Trans. Circuits Syst. I, vol. 53, no. 7, pp. 1487-1495, July 2006.
- P. Girard, L. Guiller, C. Landrault, S. Pravossoudovitch, and H. J. Wunderlich, "A modified clock scheme for a low power BIST test pattern generator," 19th IEEE Proc. VLSI Test Symp. CA, Pp. 306-311, Apr. -May 2001.
- W. Wang and S. K. Gupta, "Weighted random robust path delay testing of synthesized multilevel circuits," Proc. 12th IEEE VLSI Test Symp. Pp. 291-297, Apr. 1994.
- P. Girard, C. Landrault, V. Moreda, and S. Pravossoudovitch, "An optimized BIST test pattern generator for delay testing," Proc. 15th VLSI Test Symp. , pp. 94-100, Apr. -May 1997.
- M. Abromovici, M. A. Breuer, and A. D. Friedman, "Digital Systems Testing and Testable Design", Piscataway, NJ: IEEE Press, 1990.
- Farzad Nekoogar and Faranak Nekoogar, "From ASICs to SOCs:A Practical Approach", ISBN-10: 0-13-033857-5, ISBN-13: 978-0-13-033857-0, Pearson Education, 2003.
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