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Reseach Article

Partitioning VLSI Circuits

Published on May 2012 by Geetika, Amardeep Singh
National Workshop-Cum-Conference on Recent Trends in Mathematics and Computing 2011
Foundation of Computer Science USA
RTMC - Number 15
May 2012
Authors: Geetika, Amardeep Singh
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Geetika, Amardeep Singh . Partitioning VLSI Circuits. National Workshop-Cum-Conference on Recent Trends in Mathematics and Computing 2011. RTMC, 15 (May 2012), 26-28.

@article{
author = { Geetika, Amardeep Singh },
title = { Partitioning VLSI Circuits },
journal = { National Workshop-Cum-Conference on Recent Trends in Mathematics and Computing 2011 },
issue_date = { May 2012 },
volume = { RTMC },
number = { 15 },
month = { May },
year = { 2012 },
issn = 0975-8887,
pages = { 26-28 },
numpages = 3,
url = { /proceedings/rtmc/number15/7147-1122/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Proceeding Article
%1 National Workshop-Cum-Conference on Recent Trends in Mathematics and Computing 2011
%A Geetika
%A Amardeep Singh
%T Partitioning VLSI Circuits
%J National Workshop-Cum-Conference on Recent Trends in Mathematics and Computing 2011
%@ 0975-8887
%V RTMC
%N 15
%P 26-28
%D 2012
%I International Journal of Computer Applications
Abstract

Partitioning is a critical area of VLSI CAD. In order to build complex digital logic circuits it is often essential to sub-divide a circuit into smaller parts. Circuit partitioning plays an important role in physical design automation of very large scale integration (VLSI) chips. In VLSI circuit partitioning the problem of obtaining minimum cut is of prime importance. To enhance other criteria like power, delay and area in addition to minimum cit is included.

References
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Index Terms

Computer Science
Information Sciences

Keywords

Vlsi Circuit Partitioning delay cut Size