As we know that frequency, voltage and load capacitance plays vital role in power dissipation in VLSI circuits for achieving low power VLSI circuit we can scale any of these factors. This paper investigates the effect of supply and threshold voltages and frequency at which the VLSI chip is operated and the desired techniques for lowering the voltage and frequencies to obtain the low power consumed VLSI system. Some special techniques which can reduce the clock frequency like pipelining and parallel processing strategies for desirable propagation delays are explained in brief in this paper. By achieving low power we can fulfil needs for successful design i. e. less power, less area, less delay.

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Vlsi Frequency Scaling Cmos Parallel Processing