Low density parity check (LDPC) codes, a class of linear block code has the superior performance closer to the Shannon's limit. Non-binary LDPC (NB-LDPC) is an extension of the binary LDPC, works on the higher order Galois field. The design of efficient hardware architecture for the NB-LDPC code depends on various factors like input message format, code length, kind of modulation and the type of channel. Non-Binary LDPC codes are designed with the better performance metrics using stochastic computation. The increased computation complexity of the NB-LDPC put forth the major challenge on the hardware realization of the decoder architecture. This paper presents the design of efficient hardware architecture for NB-LDPC decoder based on stochastic computation. The designed architecture is targeted to Xilinx VIrtex device and the synthesis reports are tabulated.

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Xilinx Vertex Stochastic Decoding Latching