|National Conference on VLSI and Embedded Systems
|Foundation of Computer Science USA
|NCVES - Number 1
|Authors: B. Lokesh, K. Dushyanth, M. Malathi
B. Lokesh, K. Dushyanth, M. Malathi . 4 Bit Reconfigurable ALU with Minimum Power and Delay. National Conference on VLSI and Embedded Systems. NCVES, 1 (March 2013), 10-13.
Arithmetic Logic Unit (ALU) can be implemented in various ways using different logics. We are proposing an ALU design in which logic gates are implemented using Differential Cascode voltage switching logic (DCVSL). Manchester Carry Chain (MCC) is used to reduce the delay when addition or subtraction is performed in ALU. Using DCVSL logic gates we can obtain complemented outputs without any extra circuitry with zero static power dissipation and rail to rail swing. MCC generates carries parallel to the addition of the inputs, so when adders are cascaded one stage need not to wait for the carry input from its previous stage. Hence the carry propagation delay is reduced. Proposed ALU can perform all logical operations XOR, XNOR, AND, NAND, OR, NOR and some arithmetic operations like addition and subtraction etc. . .