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Design of High Speed Array Multiplier using BiCMOS Logic for Driving Large Load
| National Conference on VLSI and Embedded Systems |
| Foundation of Computer Science USA |
| NCVES - Number 1 |
| March 2013 |
| Authors: G. Rajeshwari, Anjo. C. A, N. Arun Kumar |
| f50e04ef-6866-488d-9a56-0db9b148b0a1 |
G. Rajeshwari, Anjo. C. A, N. Arun Kumar . Design of High Speed Array Multiplier using BiCMOS Logic for Driving Large Load. National Conference on VLSI and Embedded Systems. NCVES, 1 (March 2013), 6-9.
Abstract
In this paper we present a new combination of Bipolar and Cmos transistors which named BiCMOS and used to design a fast and low power circuits. New BiCMOS proposes and compare to the CMOS design. Proposed BiCMOS logic has advantages such as large load drive capabilities, low static power dissipation, fast switching and high input impedance. The multipliers are the main key structure for designing an energy efficient processor where a multiplier design decides the digital signal processors efficiency. In this paper, 4*4 unsigned Array multiplier architecture is designed by using BICMOS logic. Extensive simulation using Cadence to investigate the delay of propose multiplier. Simulation result shows that the propose BiCMOS has better performance in terms of delay and power consumption, in compared to CMOS counterpart. Furthermore the new design reduces the chip area because of using BiCMOS logic.
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