The design approach of FFT algorithm for floating point numbers is investigated in this paper. Using Fast Fourier Transform (FFT), the Discrete Fourier Transform (DFT) can be implement very fast. The FFT can be design by radix-2 butterfly algorithm using Decimatiom in Time (DIT) or Decimation in Frequency (DIF) methods . Using IEEE-754 Single precision floating point and Double precision floating-point format the Fast Fourier Transform (FFT) for floating point numbers can be easily computed and simulated using VHDL tools. The floating point number can support wide range of values. It can be represented using three fields sign, exponent and mantissa. The floating point Single precision format is always 32 bit and floating point Double precision format is always 64 bit. In this paper floating point addition, subtraction and multiplication algorithms is used. The IEEE-754 converter is used to convert decimal floating point number into Binary floating point format and it is also useful to verify the result. The floating point FFT processor reduce complexity of computation ,area, delay and power consumption.

1. B. Tharanidevi and R. Jayaprakash "Implementation of double precision floating point radix-2 FFT using VHDL". International Journal of Advanced Research in Electrical,Electronics and Instrumentation Engineering (An ISO 3297: 2007 Certified Organization) Vol. 2, Issue 10, October 2013
2. Hilal Kaptan1, Ali Tangel1 ,Suhap Sahin2,"FPGA Implementation of FFT Algorithm Using Floating Point Numbers" Kocaeli University, College of Engineering, Department of Electronics and Communication Engineering, Veziroglu Yerleskesi, 41040, Izmit, Turkey
3. Neha V. Mahajan, Dr. J. S. Chitode " Simple Computation of DIT FFT" International Journal of Advanced Research in Computer Science and Software Engineering Volume 4, Issue 5, May 2014 ISSN: 2277 128X
4. Afreen Fatima " Designing and Simulation of 32 Point FFT using Radix-2 algorithm for FPGA,"IOSR Journal of Elecrical and Electronics Engineering (IOSR0JEEE) e-ISSN:2320-3331, Volume9, Issue1 Ver,III (Jan 2014), PP 42-50.
5. Prasanna Palsodkar, Ajay Gurjar "Fused Floating Point Add-Subtract an Multiply-Add Unit for FFT Implementation" 2014 2nd International Conference on Devices, Circuitand Systems (ICDCS).
6. P S Raja Kumar, G. Surya Narayana Reddy "Implementation of FFT algorithm using floating point numbers in wimax communication system". International Journal of VLSI and Embedded Systems-IJVES ISSN: 2249 – 6556 "Vol 04, Article 07133; July 2013
7. Chenlu Wu , Wei Cao, Xuegong Zhou, Lingli Wang , Fang Wang , Baodi Yuan "A Reconfigurable Floating-Point FFT Architecture. "978-1-4673-6417-1/13/$31. 00 ©2013 IEEE
8. Sukhvir Kaur , Parminder Singh Jassal " Synthesis of Double Precision Float-ing Point Multiplier using VHDL "Journal of Research in Electrical and Electronics Engineering (ISTP-JREEE) . Vol 3, Issue 2, March 2014
9. Addanki Purna Ramesh, Rajesh Pattimi "High Speed Double Precision Floating Point Multiplier "International Journal of Advanced Research in Computer and Communication Engineering" Vol. 1, Issue 9, November 2012.
10. Veera Kamat Dhakankar, Prof. Sonia Kuwelkar " Design and Implementation of Pipelined Floating Point Fast Fourier Transform Processor" International Journal for Innovative Research in Science & Technology| Volume 1 | Issue 11 | April 2015 ISSN (online): 2349-6010
11. W. B. Ligon, S. McMillan, G. Mpnn, F. Stivers, and K. D Underwood "A Re-evelation of the Practicality of Floating Point Operations on FPGAs", Proceedings, IEEE Symposium on Field-Programmable Custom Computing Machines, pp. 206- 215, Napa, CA, Apr. 1998. (ICANN'99).
12. S. ?ahin, A. Kavak. , "Implementation of Floating Point Arithmetic Using an FPGA", Mathematical Methods in Engineering. Editors K. TAS, J. A. T. Machado and D. Baleanu Springer Book, 2007.
13. Asmitha Haveliya, Amity University Lucknow, India "Design And Simulation Of 32-Point FFT Using Radix-2 Algorithm For FPGA Implementation" 2012 Second International Conference on Advanced Computing & Communication Technologies.
14. H. Saleh and E. E. Swartzlander, Jr. , "A Floating-Point Fused Add-Subtract Unit," Proc. IEEE Midwest Symp. Circuits and Systems (MWSCAS), pp. 519- 522, 2008.
15. Sneha N. kherde and Meghana Hasamnis, "Efficient Design and Implementation of FFT," in International Journal of Engineering Science and Technology, 2011.
16. D. Venkatesh Babu, K. Naresh Kumar "Verilog Implementation of Floating Point FFT With Reduced Addressing Logic" International Journal of Advanced Research in Computer and Communication Engineering Vol. 3, Issue 9, September 2014
17. Brian Hickmann, Andrew Krioukov, and Michael Schulte "A Parallel IEEE P754 Decimal Floating-Point Multiplier"
18. I. S. Correa, L. C. Freitas, A. Klautau and J. C. W. A. Costa ,"VHDL Implementation of a Flexible and Synthesizable FFT Processor" IEEE Latin America Transcations, VOL. 10, NO. 1, JAN. 2012
19. J. G. Proakis, Digital signal processing: principles, algorithms, and applications, Prentice-Hall Intemational, 1996.
20. J. Bhaskar A VHDL PRIMER,Third Edition.

Floating Point Number Fft Dit Radix-2 Vhdl.