The week's pick
Random Articles
Reseach Article
Design and Implementation of NOC based Parallel AES Computation
| National Conference on Power Systems and Industrial Automation |
| Foundation of Computer Science USA |
| NCPSIA2015 - Number 1 |
| December 2015 |
| Authors: Bharati S. Kerakalamatti, Nagaraj .p |
| f04fd37e-7768-49f6-b3e0-ff3efe63ad2c |
Bharati S. Kerakalamatti, Nagaraj .p . Design and Implementation of NOC based Parallel AES Computation. National Conference on Power Systems and Industrial Automation. NCPSIA2015, 1 (December 2015), 1-4.
Abstract
In today's SOC, the number of processing cores is increasing with growth of VLSI technology. The on chip communication among multiple cores using NOC based architecture is effective than conventional bus based architecture, Since NOC has many advantages than bus based architecture mainly in terms of scalability (increase in number of nodes) and flexibility. Hence in this paper, Mesh based NOC architecture with packet switching is adopted for cryptography without virtual channel and pipelining techniques. The deterministic X-Y routing algorithm is used for routing a packet within the NOC. This paper presents a 10 -20% less area consumption NOC with AES as processing element , over previous work.
References
- L. Benini and G. De Micheli, ?Network on Chips: A New SoC Paradigm?, Proc. IEEE Transactions on Computers, Vol. 35 No. 1, January 2002, 70-78.
- P. Pratim Pande, C. Grecu, M. Jones, A. Ivanov, and R. Saleh, ?Performance evaluation and design trade-offs for network-on-chip interconnect architectures?, IEEE Transactions on Computers, vol. 54, no. 8, pp. 1025-1040, 2005.
- ARTERIS. 2005. A comparison of network-on-chip and buses. White paper.
- T. T. -O. Kwok and Y. -K. Kwok. ?On the esign,Control, and Use of A Reconfigurable Heterogeneous Multi-core System-on-a-Chip?. In IPDPS 2008, pages 1–11,Apr. 2008.
- A. Lee, NIST Special Publication 800-21, Guideline for Implementing Cryptography in the Federal Government, National Institute of Standards and Technology, ovember 1999.
- R. Yuan,S. -J. Ruan and J. G¨otz "A Practical NoC Design for Parallel DES Computation? In International symposium on VLSI Design, Automation, and Test, April – 2013.
- J. Daemen and V. Rijmen, ?The block cipher Rijndael, Smart Card research and Applications?, LNCS 1820, Springer-Verlag, pp. 288-296.
- H. C. Freitas, L. M. Schnorr, M. A. Z. Alves, and P. O. A. Navaux. ?Impact of Parallel Workloads on NoC Architecture Design?. In Parallel,Distributed and Network-Based Processing (PDP), 2010 18th Euromicro International Conference on, pages 551– 555, Feb. 2010.
- X. Li and O. Hammami. ?An Automatic Design Flowfor Data Parallel and Pipelined Signal Processing Applications on Embedded Multiprocessor with NoC: Application to Cryptography?. Int. J. Reconfig. Comput. , 2009, Jan. 2009.
- Y. S. Yang, J. H. Bahn, S. E. Lee, and N. Bagherzadeh. ?Parallel and Pipeline Processing for Block Cipher Algorithms on a Network-on-Chip?. In ITNG 2009, pages 849–854, Apr. 2009.
- Sonal S. Bhople and M. A. Gaikwad " A Comparative Study of Different Topologies for Network-On-Chip Architecture?,International Journal of Computer Applications (0975 – 8887) Recent Trends in Engineering Technology-2013
- Aline Vieira de Mello, Luciano Copello Ost,Fernando Gehm Moraes, Ney Laert Vilar Calaza ?Evaluation of Routing Algorithms on Mesh Based NoCs" Technical report series number 040 may, 2004.
Index Terms
Keywords