The week's pick
Random Articles
Reseach Article
Energy-Efficient CMOS Full Adder for Arithmetic Applications
| National Conference on Innovative Paradigms in Engineering & Technology 2013 |
| Foundation of Computer Science USA |
| NCIPET2013 - Number 8 |
| December 2013 |
| Authors: Kiran Barapatre, P. J. Suryawanshi, Sanket Lichade |
| 994a9cba-4cf6-4976-b7f5-cbaed511e5bd |
Kiran Barapatre, P. J. Suryawanshi, Sanket Lichade . Energy-Efficient CMOS Full Adder for Arithmetic Applications. National Conference on Innovative Paradigms in Engineering & Technology 2013. NCIPET2013, 8 (December 2013), 1-3.
Abstract
In this paper, we present Energy efficient CMOS full adder, which is one of the basic building blocks of a modern electronic systems design. Energy-Efficiency is one of the most required features in digital electronic systems for high-performance and/or portable applications which signify PDP, it measures the energy consumed per switching event. This paper shows that complementary CMOS is the logic style of choice for the implementation of combinational circuits, if low voltage, low power, and small power-delay products are of concern with relatively low area.
References
- A. M. Shams and M. Bayoumi, "Performance evaluation of 1-bit CMOS adder cells ", IEEE ISCAS, Orlando, Florida, May 1999, pp. I27 -130.
- A. P. Chandrakasan, S. Sheng and R. W. Brodersen, "Lowpower CMOS digital design ", IEEE JSSC, Vol. 27, April 1992, pp. 473-483.
- N. Weste and K. Eshraghian, Principles of CMOS design, A system perspective, Addison-Wesley, 1988.
- K. M. Chu and D. Pulfrey, "A comparison of CMOS circuit techniques: Differential cascode voltage switch logic versus conventional logic, "IEEE J. Solid-State Circuits, vol. SC-22, no. 4, pp. 528–532, Aug. 1987.
- K. Yano, K. Yano, T. Yamanaka, T. Nishida, M. Saito, K. Shimohigashi, and A. Shimizu, "A 3. 8 ns CMOS 16??16-b multiplier using complementary pass-transistor logic," IEEE J. Solid-State Circuits, vol. 25, no. 2, pp. 388–395, Apr. 1990.
- M. Suzuki, M. Suzuki, N. Ohkubo, T. Shinbo, T. Yamanaka, A. Shimizu, K. Sasaki, and Y. Nakagome, "A 1. 5 ns 32-b CMOS ALU in double pass-transistor logic," IEEE J. Solid-State Circuits, vol. 28, no. 11, pp. 1145–1150, Nov. 1993.
- R. Zimmerman and W. Fichtner, "Low-power logic styles: CMOS Versus pass-transistor logic," IEEE J. Solid-State Circuits, vol. 32, no. 7, pp. 1079–1090, Jul. 1997.
- N. Zhuang and H. Wu, "A new design ofthe CMOSfull adder", IEEE JSSC, Vol. 27, No. 5, May 1992, pp. 840-844
- A. M. Shams and M. Bayoumi, "A new cellfor low power adders ", Proceedings of the International MWSCAS, 1995.
- C. Chang, J. Gu, and M. Zhang, "A reviewof 0. 18-??mfull adder performances for tree structured arithmetic circuits," IEEE Trans. Very Large Scale Integr. (VLSI) Syst. , vol. 13, no. 6, pp. 686–695, Jun. 2005.
- M. Aguirre and M. Linares, "An alternative logic approach to implement high-speed low-power full adder cells," in Proc. SBCCI, Florianopolis, Brazil, Sep. 2005, pp. 166–171.
- Reto Zimmermann and Wolfgang Fichtner, Fellow, IEEE" Low-Power Logic Styles: CMOS Versus Pass-Transistor Logic" in IEEE Journal Of Solid-State Circuits, Vol. 32, No. 7, July 1997.
Index Terms
Keywords