The week's pick
Reseach Article
FPGA IMPLICATION of the LUT-SR FAMILY for UNIFORM RANDOM NUMBER GENERATION
| National Conference on Innovative Paradigms in Engineering & Technology 2013 |
| Foundation of Computer Science USA |
| NCIPET2013 - Number 7 |
| December 2013 |
| Authors: M. V. Vyawahare, Rita Rawate |
| 66dd45be-fb01-4700-8852-8bf988ef52fd |
M. V. Vyawahare, Rita Rawate . FPGA IMPLICATION of the LUT-SR FAMILY for UNIFORM RANDOM NUMBER GENERATION. National Conference on Innovative Paradigms in Engineering & Technology 2013. NCIPET2013, 7 (December 2013), 19-22.
Abstract
Field-programmable gate array (FPGA) optimized random number generators (RNGs) can take advantage of bitwise operations and FPGA-specific features, hence they are more resource-efficient than software-optimized RNGs. This paper describes a type of RNG called a LUT-SR RNG, which takes advantage of bitwise XO R operations and the ability to configure lookup tables (LUTs) into decoders & shift registers of varying lengths. This provides good quality compared to others. The LUT-SR generators is implemented by using VHDL (very high speed integrated circuit hardware description language).
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