Scaling of conventional CMOS devices has reduced the device dimensions from 10 mm in 1970s to 0.1 ?m in a present day. According to ITRS (i.e. International Technology Roadmap for Semiconductors ) we are going to face the brick wall in 2015 if we continue in the same development speed. This will not be possible for us to maintain the pace forecasted by Moore.(Moore?s law) This is because of the fundamental limitations of device parameter dimensions due to which performance is degrading in several ways. To overcome this and go ahead in technology , one must look into new devices those can be scaled down to come up with other solutions. Either it should be possible to go ahead by again reducing the device dimensions in some way or we have to reduce the circuit overhead with less complexity. Solution to this might be : MVL i.e. Multivalued Logic & TFET i.e. Tunnel Field Effect Transistor.[1] This report presents a novel design of Ternary Logic Gates & arithmetic circuits using TFET.

1. A. Lin, N. Patil, K. Ryu, A. Badmaev, L. G. De Arco,C. Zhou, S. Mitra, and H.-S. P. Wong, “Threshold voltage and on–off ratio tuning for multiple tube carbon nanotube FETs,” IEEE Trans. Nanotechnol., vol. 8, no. 1, pp. 4–9, Jan. 2009.
2. Daniel Rairigh, “Limits of CMOS Technology Scaling and Technologies Beyond-CMOS”, IEEE, Nov. 21, 2009 .
3. Robert R McCormick school of engineering and applied science, “Nanoscale cmos”, Department of material science, Northwestern university, USA, 2009.
4. Low power CMOS circuit design : by Kaushik Roy
5. S. Thompson, P. Packan, and M. Bohr, "MOS Scaling: Transistor Challenges in the 21st Century,” Source:Intel Technology Journal, v.Q3, p.1-19, 1998. http://developer.intel.com/technology/itj/q319- 98/articles/art_3.htm
6. R.S. Muller, T.I. Kamins and M. Chan, “Device Electronics for Integrated Circuits, Third Edition,” John Wiley & Sons, Inc., 2003.
7. CNTFET based design of Ternary Logic Gates & Arithmetic Circuits : by Sheng Lin, Student Member, IEEE, Yong-Bin Kim, Senior Member, IEEE, and Fabrizio Lombardi, Fellow, IEEE.
8. Aspects of balance Ternary Arithmetics implemented using CMOS charged semiconducting Gate Devices: by Henning Gundersen , Institute of infermatics , University of Oslo.
9. A Novel CNTFET-Based Ternary Logic Gate Design : by Sheng Lin, Yong-Bin Kim and Fabrizio Lombardi , Northeastern University Boston, MA, USA.

CMOS ITRS TFET MVL