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3.3GHz Phase locked loop with four multiple output using 45nm CMOS Technology

Published on March 2012 by Ujwala A. Belorkar, S.A. Ladhake
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2nd National Conference on Innovative Paradigms in Engineering and Technology (NCIPET 2013)
Foundation of Computer Science USA
NCIPET - Number 6
March 2012
Authors: Ujwala A. Belorkar, S.A. Ladhake
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Ujwala A. Belorkar, S.A. Ladhake . 3.3GHz Phase locked loop with four multiple output using 45nm CMOS Technology. 2nd National Conference on Innovative Paradigms in Engineering and Technology (NCIPET 2013). NCIPET, 6 (March 2012), 16-20.

@article{
author = { Ujwala A. Belorkar, S.A. Ladhake },
title = { 3.3GHz Phase locked loop with four multiple output using 45nm CMOS Technology },
journal = { 2nd National Conference on Innovative Paradigms in Engineering and Technology (NCIPET 2013) },
issue_date = { March 2012 },
volume = { NCIPET },
number = { 6 },
month = { March },
year = { 2012 },
issn = 0975-8887,
pages = { 16-20 },
numpages = 5,
url = { /proceedings/ncipet/number6/5233-1045/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Proceeding Article
%1 2nd National Conference on Innovative Paradigms in Engineering and Technology (NCIPET 2013)
%A Ujwala A. Belorkar
%A S.A. Ladhake
%T 3.3GHz Phase locked loop with four multiple output using 45nm CMOS Technology
%J 2nd National Conference on Innovative Paradigms in Engineering and Technology (NCIPET 2013)
%@ 0975-8887
%V NCIPET
%N 6
%P 16-20
%D 2012
%I International Journal of Computer Applications
Abstract

This paper present area efficient layout design for 3.3GigaHertz (GHz) Phase Locked loop (PLL) with four multiple output. Effort has been taken to design Low Power Phase locked loop with multiple output, using VLSI technology. VLSI Technology includes process design, trends, chip fabrication, real circuit parameters, circuit design, electrical characteristics, configuration building blocks, switching circuitry, translation onto silicon, CAD and practical experience in layout design. The proposed PLL is designed using 45 nm CMOS/VLSI technology with microwind 3.1. This software allows designing and simulating an integrated circuit at physical description level. The main novelties related to the 45 nm technology are the high-k gate oxide, metal gate and very low-k interconnect dielectric. The effective gate length required for 45 nm technology is 25nm. Low Power (0.211miliwatt) phase locked loop with four multiple outputs as PLL8x, PLL4x, PLL2x, & PLL1x of 3.3 GHz, 1.65 GHz, 0.825 GHz, and 0.412 GHz respectively is obtained using 45 nm VLSI technology.

References
  1. E. Sicard, Syed Mahfuzul Aziz, “introducing 45 nm technology in Microwind3,” microwind application note.
  2. Navid Azizi, Student Member, IEEE, Muhammad M. Khellah, Member, IEEE, Vivek K. De, Senior Member, IEEE,and Farid N. Najm, Fellow, IEEE,”Aware Low-Power Design and Block.” IEEE transactions on very large scale integration (vlsi) systems, vol. 15, no. 7, july 2007
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  8. Oscal T. – C. Chen “A power efficient wide range phase locked loop” IEEE journal of solid state circuits vol. 37 No. 1 January 2002.
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Index Terms

Computer Science
Information Sciences

Keywords

phase-locked loop (PLL) high performance voltage-controlled oscillator (VCO) 45nm technology multiple output low power