We apologize for a recent technical issue with our email system, which temporarily affected account activations. Accounts have now been activated. Authors may proceed with paper submissions. PhDFocusTM
CFP last date
20 December 2024
Reseach Article

Review of Junctionless transistor using CMOS technology and MOSFETs

Published on March 2012 by Shridhar R. Sahu
2nd National Conference on Innovative Paradigms in Engineering and Technology (NCIPET 2013)
Foundation of Computer Science USA
NCIPET - Number 4
March 2012
Authors: Shridhar R. Sahu
643cc346-1a06-4e19-a51b-8ff2e8e2adb2

Shridhar R. Sahu . Review of Junctionless transistor using CMOS technology and MOSFETs. 2nd National Conference on Innovative Paradigms in Engineering and Technology (NCIPET 2013). NCIPET, 4 (March 2012), 8-11.

@article{
author = { Shridhar R. Sahu },
title = { Review of Junctionless transistor using CMOS technology and MOSFETs },
journal = { 2nd National Conference on Innovative Paradigms in Engineering and Technology (NCIPET 2013) },
issue_date = { March 2012 },
volume = { NCIPET },
number = { 4 },
month = { March },
year = { 2012 },
issn = 0975-8887,
pages = { 8-11 },
numpages = 4,
url = { /proceedings/ncipet/number4/5215-1027/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Proceeding Article
%1 2nd National Conference on Innovative Paradigms in Engineering and Technology (NCIPET 2013)
%A Shridhar R. Sahu
%T Review of Junctionless transistor using CMOS technology and MOSFETs
%J 2nd National Conference on Innovative Paradigms in Engineering and Technology (NCIPET 2013)
%@ 0975-8887
%V NCIPET
%N 4
%P 8-11
%D 2012
%I International Journal of Computer Applications
Abstract

Transistors are the fundamental building blocks of modern electronic devices and all existing transistors contain semiconductor junctions. Junctionless transistor is a uniformly doped nanowire without junctions with a wrap-around gate. As the distance between junctions in modern devices drops below 10nm, extraordinarily high doping concentration gradients become necessary. Junctionless transistors could therefore help chipmakers continue to make smaller devices. Here, in this paper presented a new type of transistor in which there are no junctions and no doping concentration gradients. They have near-ideal sun threshold slope, extremely low leakage currents, and less degradation of mobility with gate voltage and temperature than classical transistors.

References
  1. Chun-Yu Chen1, Jyi-Tsong Lin1, Meng-Hsueh Chiang2, and Keunwoo Kim3 “High-Performance Ultra-Low Power Junctionless Nanowire FET on SOI Substrate in Subthreshold Logic Application” 1National Sun Yat-Sen University., Kaohsiung 804, Taiwan ROC, 2National Ilan University., I-Lan 260, Taiwan ROC, 3IBM T. J. Watson Research Center, Yorktown Heights, NY 10598, USA
  2. Jean-Pierre Colinge, Chi-Woo Lee, Aryan Afzalian, Nima Dehdashti Akhavan, Ran Yan, Isabelle Ferain, Pedram Razavi, Brendan O?Neill, Alan Blake, Mary White, Anne-Marie Kelleher, Brendan McCarthy and Richard Murphy: “Nanowire transistors without junctions”, Nature nanotechnology.
  3. J.P. Colinge, C.W. Lee, A. Afzalian, N. Dehdashti, R. Yan, I. Ferain, P. Razavi, B. O?Neill, A. Blake, M. White, A.M. Kelleher, B. McCarthy and R. Murphy “SOI Gated Resistor: CMOS without junctions” Tyndall National Institute, University College Cork, Lee Maltings, Prospect Row, Cork, Republic of Ireland.
  4. Chan-Hoon Park, Myung-Dong Ko, Ki-Hyun Kim, Chang-Woo Sohn, Chang Ki Baek, Yoon-Ha Jeong and Jeong-Soo Lee “Comparative Study of Fabricated Junctionless and Inversion-mode N anowire FE Ts”. POSTECH, Pohang, Gyeongbuk, 790-784, Korea.
  5. Arash Dehzangi, Farhad Larki, E.B. Saion, Sabar D. Hatagalung, Makarimi Abdullah, M.N. Hamidon and Jumiah Hassan “Study the Characteristic of P-Type Junction-Less Side Gate Silicon Nanowire Transistor Fabricated by Atomic Force Microscopy Lithography” American Journal of Applied Sciences 8 (9): 872-877, 2011 ISSN 1546-9239 © 2011 Science Publications
  6. Chi-Woo Lee, Adrien Borne, Isabelle Ferain, Aryan Afzalian, Member, IEEE, Ran Yan, Nima Dehdashti Akhavan, Pedram Razavi, and Jean-Pierre Colinge, Fellow, IEEE, “High-Temperature Performance of Silicon Junctionless MOSFETs” IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 3, MARCH 2010.
  7. Twinkal Solankia, Nilesh Parmar “ A Review paper: A Comprehensive study of Junctionless transistor”, National Conference on Recent Trends in Engineering & Technology.
  8. Chih-Hsuan Tai, Jyi-Tsong Lin, Yi-Chuen Eng, and Po-Hsieh Lin “A Novel High-Performance Junctionless Vertical MOSFET Produced on Bulk-Si Wafer” Dept. of Electrical Engineering, National Sun Yat-Sen University, Kaohsiung 80424, Taiwan R.O.C.
Index Terms

Computer Science
Information Sciences

Keywords

Gated resistor Junctionless transistor Silicon nanowire FET Ebeam lithography and AFM