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Current Starved Voltage Controlled Oscillator for PLL Using 0.18?m CMOS Process
| 2nd National Conference on Innovative Paradigms in Engineering and Technology (NCIPET 2013) |
| Foundation of Computer Science USA |
| NCIPET - Number 3 |
| March 2012 |
| Authors: Rashmi K Patil, Vrushali G Nasre |
| 8d2ae817-e1df-40ba-8a32-74b1b81fe573 |
Rashmi K Patil, Vrushali G Nasre . Current Starved Voltage Controlled Oscillator for PLL Using 0.18?m CMOS Process. 2nd National Conference on Innovative Paradigms in Engineering and Technology (NCIPET 2013). NCIPET, 3 (March 2012), 23-25.
Abstract
A five stage current starved Voltage Controlled Oscillator (CMOS VCO) is designed in this paper. The design is implemented in Tanner environment with high oscillation frequency and low power consumption. Oscillation frequency of the designed VCO ranges from 25.70 MHz to 222.53 MHz. The circuit is simulated using 180nm SCN018 Technology. Simulation results reported that the power consumption is 58.47uA @ 1.8V VDD. Design procedures and simulation results are illustrated. This design is suitable for PLL as a frequency multiplier.
References
- B .Razvi, Design of ANALOG CMOS Integrated Circuits, McGraw- Hill, 2001
- H. Z. Lei, High Frequency Phase-Locked Loop Design and Simulation, Thesis (B.S.), California Polytechnic State University, 2004. Microfiche. San Luis Obispo, Calif. : MPI Microfilm Service,2004.
- R. Jacob Baker, Harry W. Li & David E. Boyce, CMOS Circuit Design Layout, and Simulation, IEEE Press, 2002.
- Haripriya Janardhan,Mahmoud Fawzy Wagdy, “Design of a 1GHz Digital PLLUsing 0.18?m CMOS Technology” in IEEE 2006 Third International Conference on Information Technology: New Generations (ITNG'06)
- H. Cong, Simulations of Phase-Lock Loop in Communication Systems, College of Engineering,California State Polytechnic University, Pomona,CA.
- GEORGE TOM VARGHESE, Phase Locked Loop Design as a Frequency Multiplier, Thesis Department of Electronics and Communication Engineering National Institute Of Technology Rourkela, India, 2007-2009
- Y. Limdulpaiboon, “A Phase-Locked Loop Circuit Design and Implementation”, Thesis (B.S.),California Polytechnic State University, Microfiche. San Luis Obispo, Calif. MPI Microfilm Service, 2003.
- S. Brown and Z. Vranesic, Fundamentals of Digital Logic with VHDL Design, ISBN 0071161686, Dept. of Elec. & Comp. Engineering, University of Toronto, 2000
- M. Suresh, Design of a Testable Jitter-Free Digital Phase-Locked Loop, Thesis (M.S.), Santa Clara University, School of Engineering, 1996.
- D. H. Wolaver, Phase-Locked Loop Circuit Design, N.J, ISBN 0136627439, c1991.
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