The week's pick
Reseach Article
Placement Compelled Steering Algorithm for Wire length Minimization in FPGA
| National Conference on Information and Communication Technologies |
| Foundation of Computer Science USA |
| NCICT2015 - Number 2 |
| September 2015 |
| Authors: Khaavya S.l., S. Umamaheswari |
| d93d8041-323f-4d66-809c-2a3140f71d5b |
Khaavya S.l., S. Umamaheswari . Placement Compelled Steering Algorithm for Wire length Minimization in FPGA. National Conference on Information and Communication Technologies. NCICT2015, 2 (September 2015), 32-35.
Abstract
Placements of logical blocks in FPGA use many optimization algorithms in heuristic manner. Main objective is to provide minimization in wire length during the task placement inside Reconfigurable FPGAs, which will decrease the area, power and delay and increase the speed of execution. Optimization algorithms are applied in the Benchmark circuits and the results are compared. Due to the technological advancement, density of the devices increases so that necessitates improvement in minimization of wire length. Hence this project, proposes an optimum solution for wire length minimization.
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