CFP last date
20 January 2025
Call for Paper
February Edition
IJCA solicits high quality original research papers for the upcoming February edition of the journal. The last date of research paper submission is 20 January 2025

Submit your paper
Know more
The week's pick
Responsive image
SFLA-Based Line Balancing and Task Optimization in Master-Slave Controlled Hanger Transportation Systems for Garment Production

Duc Hoang Nguyen
Random Articles
Reseach Article

Design of Multiplier based Low Power PID Controllers

Published on September 2015 by V. Priya, A. Abinaya
journal_cover_thumbnail

National Conference on Information and Communication Technologies
Foundation of Computer Science USA
NCICT2015 - Number 1
September 2015
Authors: V. Priya, A. Abinaya
361b0849-0b63-42d7-acf7-665331c801c0

V. Priya, A. Abinaya . Design of Multiplier based Low Power PID Controllers. National Conference on Information and Communication Technologies. NCICT2015, 1 (September 2015), 34-37.

@article{
author = { V. Priya, A. Abinaya },
title = { Design of Multiplier based Low Power PID Controllers },
journal = { National Conference on Information and Communication Technologies },
issue_date = { September 2015 },
volume = { NCICT2015 },
number = { 1 },
month = { September },
year = { 2015 },
issn = 0975-8887,
pages = { 34-37 },
numpages = 4,
url = { /proceedings/ncict2015/number1/22350-1541/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Proceeding Article
%1 National Conference on Information and Communication Technologies
%A V. Priya
%A A. Abinaya
%T Design of Multiplier based Low Power PID Controllers
%J National Conference on Information and Communication Technologies
%@ 0975-8887
%V NCICT2015
%N 1
%P 34-37
%D 2015
%I International Journal of Computer Applications
Abstract

The increasing industrial growth needs its system to be fully controllable. Such control systems are almost composed of VLSI components such as adders, multipliers and accumulators. This paper analyzes two MAC units with array, booth algorithms and those blocks are incorporated in PID controller architecture. Comparisons are made with power consumption of each architecture. The simulations are done in Modelsim and power results are synthesized using Xilinx ISE. The results suggest that the PID controller with booth based MAC unit and PID architecture consumes less power when compared to array based architectures.

References
  1. Liguo Qu,Yourui Huang and Liuyi Ling "Design and implementation of intelligent PID controller based on FPGA", IEEE computer society, 2009,pp. 511-515.
  2. Jaoa Lima,Ricardo Menotti,M. P. Cardoso and Eduardo Marques "A methodology to design FPGA based PID controllers", IEEE international conference, Oct 2006, pp. 2577-2583.
  3. Mayank Nema and Murali Manohar Nema "PID controller analysis based on Different Addition methods", International journal of Emerging technology and advanced Engineering, Nov 2013, Vol 3, Issue 11, pp. 398-403.
  4. Sumit Vaidya and Deepak Dandekar "Delay-Power performance comparison of Multipliers in VLSI circuit Design", International journal of Computer Networks & Communication, Vol 2, No 4, Jul 2010, pp. 47-56.
  5. H. G. Rangaraju,H. S. Arpitha and K. N. Muralidhara "Design of Efficient Reversible Multiply Accumulate (MAC) Unit", International Journal of Computer Applications, Vol. 85, No. 16,Jan 2014,pp. 1-12.
  6. A. K. Oudjida,N. Chaillet,A. Liacha,M. L. Berrandjia and M. Hamerlain "Design of high speed and low power finite word length PID controllers", Control Theory Tech, Vol. 12, No. 1, Feb. 2014, pp. 68-83.
  7. Young Ho Seo and Dong Wook Kim "A New VLSI Architecture of parallel multiplier-Accumulator based on Radix-2 Modified Booth Algorithm",IEEE Transactions on VLSI Systems, Vol. 18, No. 2, Feb 2010,pp. 201-208.
  8. Rajesh Nema,Rajeev Thakur and Ruchi Gupta "Design & Implementation of FPGA Based On PID Controller, IJIES, Vol. 1, Issue. 2, Jan 2013, pp. 14-16.
  9. Shiann Rong Kuang, Jiun Ping Wang and Cang Yuan Guo "Modified Booth Multipliers With a Regular Partial Product Array", IEEE Transactions on Circuits and Systems, Vol. 56,No. 5, May 2009, pp. 404-408.
Index Terms

Computer Science
Information Sciences

Keywords

Multiply-accumulate (mac) Array Multiplier Booth Multiplier Proportional-integral-derivative Controllers (pid)