Modern Digital signal processing and image processing applications are aiming towards energy efficiency. The prime arithmetic operation performed for these processes is multiplication. Hence energy efficiency of multiplication is critical. Since many digital applications use fixed- point arithmetic, it exhibits computational error tolerance. In this brief, a multiplier is proposed that can trade-off computational accuracy with energy consumption. Segmenting the original operands with significant bits and performing the multiplication only for those segments is the main principle. The proposed method of approximate multiplier consumes lesser power and hence notably lesser energy with average computational error of ~1%, when compared to the existing approximate multipliers with similar principle. Further optimization of the proposed multiplier is also done which improves the average computational accuracy along with a considerable reduction in the area consumed by the proposed multiplier.

1. Srinivasan Narayanamoorthy, Hadi Asghari Moghaddam, Zhenhong Liu, Taejoon Park, and Nam Sung Kim, July 2014, "Energy-Efficient Approximate Multiplication for Digital Signal Processing and Classification Applications", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Early Access Articles, pp. 1 – 5.
2. Zdenek Vasicek and Lukas Sekanina, April 2014, "Evolutionary Design of Approximate Multipliers under Different Error Metrics", Design and Diagnostics of Electronic Circuits & Systems, 17th International IEEE Symposium, pp. 135 – 140.
3. K. S. Ganesh Kumar, J. Deva Prasannam, M. Anitha Christy, March 2014, "Analysis of Low Power, Area and High Performance Multipliers for DSP applications", International Journal of Emerging Technology and Advanced Engineering, Volume 4, Issue 3,pp. 278-382.
4. Vinay K. Chippa, Srimat T. Chakradhar, Kaushik Roy and Anand Raghunathan, May- June 2013, "Analysis and Characterization of Inherent Application Resilience for Approximate Computing", IEEE Design Automation Conference (DAC), 2013 50th ACM / EDAC / IEEE, pp. 1- 9.
5. Jie Han, Michael Orshansky, May 2013, "Approximate Computing: An emerging Paradigm for Energy-Efficient Design", Test Symposium (ETS), 2013 18th IEEE European, pp. 1-6.
6. A. Kishore Kumar, D. Somasundareswari, V. Duraisamy and T. Shunbaga Pradeepa, February 2013 , "Design of Low Power Multiplier with Energy Efficient Full Adder Using DPTAAL" , Hindawi Publishing Corporation,VLSI Design, Volume 2013, pp. 1-9.
7. P. Kulkarni, P. Gupta, and M. Ercegovac, January 2011 "Trading accuracy for power with an under designed multiplier architecture," in Proc. 24th IEEE Int. Conf. VLSI Design (VLSID), pp. 346–351.
8. C. H. Chang and R. K. Satzoda, December 2010, "A low error and high performance multiplexer-based truncated multiplier," IEEE Trans. Very Large Scale Integr. (VLSI) Syst. , vol. 18, no. 12, pp. 1767–1771.
9. V. K. Chippa, D. Mohapatra, A. Raghunathan, K. Roy, and S. T. Chakradhar, June 2010, "Scalable effort hardware design: Exploiting algorithmic resilience for energy efficiency," in Proc. 47th IEEE/ACM Design Autom. Conf. , pp. 555–560.
10. Sjalander. M, Larsson-Edefors,P. , Aug. 31 2008-Sept. 3 2008, "High-speed and low-power multipliers using the Baugh-Wooley algorithm and HPM reduction tree", Electronics, Circuits and Systems, 2008, ICECS-2008. 15th IEEE International Conference, pp. 33 – 36.

Vlsi Embedded Systems Integrated Circuits Dsp