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A Segmented Current Steering DAC for Wireless Application

Published on November 2011 by Vivek P. Landge, Abhijit B. Maidamwar
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2nd National Conference on Information and Communication Technology
Foundation of Computer Science USA
NCICT - Number 8
November 2011
Authors: Vivek P. Landge, Abhijit B. Maidamwar
dfc6dac7-2566-482b-8490-220974d00b04

Vivek P. Landge, Abhijit B. Maidamwar . A Segmented Current Steering DAC for Wireless Application. 2nd National Conference on Information and Communication Technology. NCICT, 8 (November 2011), 28-31.

@article{
author = { Vivek P. Landge, Abhijit B. Maidamwar },
title = { A Segmented Current Steering DAC for Wireless Application },
journal = { 2nd National Conference on Information and Communication Technology },
issue_date = { November 2011 },
volume = { NCICT },
number = { 8 },
month = { November },
year = { 2011 },
issn = 0975-8887,
pages = { 28-31 },
numpages = 4,
url = { /proceedings/ncict/number8/4243-ncict063/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Proceeding Article
%1 2nd National Conference on Information and Communication Technology
%A Vivek P. Landge
%A Abhijit B. Maidamwar
%T A Segmented Current Steering DAC for Wireless Application
%J 2nd National Conference on Information and Communication Technology
%@ 0975-8887
%V NCICT
%N 8
%P 28-31
%D 2011
%I International Journal of Computer Applications
Abstract

This paper presents a CMOS Nyquist rate Current Steering DAC using segmented architecture for wireless application. Segmentation is used to improve the dynamic behavior of the converter but comes at a cost. The proposed DAC adapts 8-4 segmentation architecture to achieve high speed. The DAC is realized in 0.18-μm CMOS process and the power supply used is 1.8V. Cadence Virtuoso Schematic editor is used for drawing the schematic of various circuits and the circuits are simulated using Virtuoso circuit simulator. The dac has been simulated and found to be working satisfactorily.

References
  1. M. Gustavsson, J. Wikner, and N. Tan, CMOS Data Converter for Communication. Kluwer Academic Publishers, 2002.
  2. J. Rabaey, Digital Integrated Circuits – A Design Perspective, Prentice Hall, Upper Saddle River, NJ, USA, 1996, ISBN 0-13-394271-6..
  3. M.J.M Pelgrom, A.C.J. Duinmaijer, and A.P.G. Welbers, “Matching Properties of MOS Transistors,” IEEE J. of Solid-State Circuits, vol. 24, no. 5, pp. 1433-9, Oct. 1989.
  4. Douglas Mercer, “A Study Of Error Sources In Current Steering Digital-to-Analog Converters”, IEEE 2004 Custom Integrated Circuits Conference.
  5. J. Wikner and N. Tan, “A CMOS Digital-to-Analog Converter Chipset for Telecommunication,”IEEE Magazine on Circuits and Devices, Vol. 13, No. 5, pp. 11-16, Sep. 1997.
  6. K.O. Andersson and J.J. Wikner, "Modeling of the Influence of Graded Element Matching Errors in CMOS Current-Steering DACs," in Proc. of the 17th NorChip Conf., NORCHIP’99, Oslo,Norway, Nov. 8-9, 1999.
  7. Ming-Chin Chen, Chia-Chun Liu, and Ching-Cheng Tien, “A 10-bit 160-MSPS 2.5-V Segmented Current Steering CMOS DAC for WLAN Applications ”, 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits(AP-ASIC2004)/ Aug. 4-5, 2004.
  8. Nicola Ghittori, Andrea Vigna, Piero Malcovati, Stefano D’Amico, and Andrea Baschirotto, “1.2-V Low-Power Multi-Mode DAC+Filter Blocks for Reconfigurable (WLAN/UMTS, WLAN/Bluetooth) Transmitters”, IEEE Journal Of Solid-State Circuits, Vol. 41, No. 9, September 2006.
  9. Gaurav Raja and Basabi Bhaumik, “16-bit Segmented Type Current Steering DAC for Video Applications”, Proceedings of the 19th International Conference on VLSI Design (VLSID’06).
  10. Matthew Gast, 802.11 Wireless Networks, The Definitive Guide- Second Edition, O’reilly Publishing Company. ISBN 0-596-19952-3
  11. Jim Geier, Wireless LANs, Second Edition, Sams Publisher, ISBN 0-072- 32058-4
  12. Ken Martin, “Analog Integrated Circuit Design”, John Wiley and Son’s Inc.
  13. Ramji Prasad and Richard van Nee, “OFDM for Wireless Multimedia Communications”, Artech House universal personal communication Series
  14. Jacob Wikner, “Studies on CMOS Digital-To-Analog Converters ”, Linköping Studies in Science and Technology Dissertation No. 667, ISBN91-7219-910-5.
Index Terms

Computer Science
Information Sciences

Keywords

DAC Unit current source DNL glitch clock skew clock feedthrough