Network-on-Chip (NoC) has been proposed as an alternative to bus-based schemes to achieve high performance and scalability in System-on-Chip (SoC) design. Performance evaluation of On-Chip Interconnect (OCI) architectures is widely based on simulation which becomes computationally expensive, especially for largescale NoCs. In this paper, we study the various NOC architectures i.e. Virtual Channel Router Design, Wormhole Router Design, Circuit Switched Router Design.

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Networks-on-Chip (NoCs) Systems-on-Chip(SoCs) throughput latency