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A Novel Full Adder with High Speed Low Area
| 2nd National Conference on Information and Communication Technology |
| Foundation of Computer Science USA |
| NCICT - Number 1 |
| November 2011 |
| Authors: G.Shyam Kishore |
| cf9ede60-23b9-4f73-9237-9ad9874b1dc3 |
G.Shyam Kishore . A Novel Full Adder with High Speed Low Area. 2nd National Conference on Information and Communication Technology. NCICT, 1 (November 2011), 34-37.
Abstract
In most of the digital systems adder lies in the critical path that effects the overall speed of the system. So enhancing the performance of the 1-bit full adder cell is the main design aspect. The paper proposes the novel design of a 3T XOR gate combining complementary CMOS with pass transistor logic. The design has been compared with earlier proposed 4T and 6T XOR gates and a significant improvement in silicon area and power-delay product has been obtained. An eight transistor full adder has been designed using the proposed three transistor XOR gate. Compared t o the earlier designed 10, 14, 16 transistor full adder, the proposed adder shows a significant improvement in silicon area and power delay product.
References
- M. Hosseinzadeh, S.J. Jassbi, and Keivan Navi, ―A NoveMultiple Valued Logic OHRNS Modulo rn Adder Circuit‖ International Journal of Electronics, Circuits and Systems, Vol1, No. 4, Fall 2007, pp. 245-249.
- D. Radhakrishnan, ―Low-voltage low-power CMOS fulladder,‖ in Proc. IEE Circuits Devices Syst., vol. 148, Feb2001, pp. 19-24.
- Y. Leblebici, S.M. Kang, CMOS Digital Digital IntegratedCircuits, Singapore: Mc Graw Hill, 2nd edition, 1999, Ch. 7.
- J. Wang, S. Fang, and W. Feng, ―New efficient designfor XOR and XNOR functions on the transistor level,‖ IEEE J. Solid-State Circuits, vol. 29, no. 7, Jul. 1994, pp. 780–786.
- H. T. Bui, A. K. Al-Sheraidah, and Y.Wang, ―New 4transistor XOR and XNOR designs,‖ in Proc. 2nd IEEE AsiaPacific Conf. ASICs, 2000, pp. 25–28.
- H.T. Bui, Y. Wang, Y. Jiang , ―Design and analysis of 10transistor full adders using novel XOR–XNOR gates,‖ inProc. 5th Int. Conf. Signal Process., vol. 1, Aug. 21–25, 2000,pp. 619–622.
- H. T. Bui, Y. Wang, and Y. Jiang, ―Design and analysis of low-power 10-transistor full adders using XOR-XNORgates,‖ IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 49, no. 1, Jan. 2002, pp. 25–30.
- A. M. Shams, T. K. Darwish, and M. A. Bayoumi, Performance analysis of low-power 1-bit CMOS full adder cells,‖ IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 10, no. 1, Feb. 2002, pp. 20–29.
- K.-H. Cheng and C.-S. Huang, ―The novel efficient design of XOR/XNOR function for adder applications,‖ in Proc. IEEEInt. Conf. Elect., Circuits Syst., vol. 1, Sep. 5–8, 1999, pp. 29– 32.
- H. Lee and G. E. Sobelman, ―New low-voltage circuits for XOR and XNOR,‖ in Proc. IEEE Southeastcon, Apr. 12–14, 1997, pp. 225–229.
- M. Vesterbacka, ―A 14-transistor CMOS full adder with full voltage swing nodes,‖ in Proc. IEEE Worksh. Signal Process. Syst., Oct. 20–22, 1999, pp. 713–722.
- G.A. Ruiz, M. Granda, ―An area-efficient static CMOS carry-select adder based on a compact carry look-ahead unit, Microelectronics Journal, Vol. 35, No. 12, 2004, pp. 939-944.
- R. Zimmermann and W. Fichtner, ―Low-power logic styles: CMOS versus pass-transistor logic,‖ IEEE J. SolidState Circuits, vol.32, July 1997, pp.1079–90.
- N. Weste and K. Eshraghian, Principles of CMOS VLSI Design, A System Perspective. Reading, MA: AddisonWesley, 1993.
- N. Zhuang and H. Wu, ―A new design of the CMOS full adder,‖ IEEE J. Solid-State Circuits, vol. 27, no. 5, May 1992, pp. 840–844.
- E. Abu-Shama and M. Bayoumi, ―A new cell for low power adders,‖ in Proc. Int. Midwest Symp. Circuits Syst., 1995, pp. 1014–1017.
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