The week's pick
Reseach Article
A Novel Full Adder with High Speed Low Area
| 2nd National Conference on Information and Communication Technology |
| Foundation of Computer Science USA |
| NCICT - Number 1 |
| November 2011 |
| Authors: G.Shyam Kishore |
| cf9ede60-23b9-4f73-9237-9ad9874b1dc3 |
G.Shyam Kishore . A Novel Full Adder with High Speed Low Area. 2nd National Conference on Information and Communication Technology. NCICT, 1 (November 2011), 34-37.
Abstract
In most of the digital systems adder lies in the critical path that effects the overall speed of the system. So enhancing the performance of the 1-bit full adder cell is the main design aspect. The paper proposes the novel design of a 3T XOR gate combining complementary CMOS with pass transistor logic. The design has been compared with earlier proposed 4T and 6T XOR gates and a significant improvement in silicon area and power-delay product has been obtained. An eight transistor full adder has been designed using the proposed three transistor XOR gate. Compared t o the earlier designed 10, 14, 16 transistor full adder, the proposed adder shows a significant improvement in silicon area and power delay product.
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