The sensor network has become an important aspect in the day today life because of its wide range of application from medical field to the military application. The raw data from sensor node are of large quantity and hence it is necessary to store these data bits. In this paper, design of optimized SRAM array for low power applications is implemented. SRAM cell is designed using 8T. In this, transmission gate is used as access transistor to increase write-ability and decrease the power dissipation. The peripheral circuits are chosen to construct the SRAM array. Simulation are carried out using 180nm technology and result show that the reading and writing of data takes place correctly.

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Sram Sensor Network Static Noise Margin.