National Conference “Electronics, Signals, Communication and Optimization" |
Foundation of Computer Science USA |
NCESCO2015 - Number 3 |
September 2015 |
Authors: Lankesh, K C Narasimhamurthy |
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Lankesh, K C Narasimhamurthy . Hardware Implementation of Single Bit Error Correction and Double Bit Error Detection through Selective Bit Placement for Memory. National Conference “Electronics, Signals, Communication and Optimization". NCESCO2015, 3 (September 2015), 5-9.
Hamming codes are widely used for the single bit error correction double bit error detection (SEC-DED) which occurred during data transmission process. This paper presents an enhanced detection of double adjacent bit errors and correcting all possible single bit errors in Hamming codes through selective bit placement technique for memory application. Soft errors occur due to the radiation particles which affects the memory elements. These soft errors cause flipping of single bit or more often adjacent bits in the memory. Proposed technique improves the probability of detecting double adjacent bit errors and also provides a simple method of detecting double adjacent bit errors as compared to convolution coding through interleaving which is complex and requires higher memory. Hamming (12, 8) is implemented on hardware using RL 78 (G13) Microcontroller.