National Conference on Electronics, Signals and Communication |
Foundation of Computer Science USA |
NCESC2017 - Number 4 |
July 2018 |
Authors: Veenashree Hiremath |
c3418432-9cb0-434d-91d3-ae55c0f05f1a |
Veenashree Hiremath . Design and Performance Evaluation of Reconfigurable Architecture of FIR Filter for Signal Processing Applications. National Conference on Electronics, Signals and Communication. NCESC2017, 4 (July 2018), 4-6.
Finite impulse response (FIR) filters are tremendously used in signal processing applications like RADAR processing, noise cancellation, biomedical imaging, removing DC component in signal etc. Most of Digital signal processing algorithm such as FFT,FIR and IIR are now implemented on FPGA because it offers very attractive solutions than any other in terms area ,power and speed. Reconfigurable architecture used in this paper is Distributed arithmetic . Here DA based FIR filter implemented on vertex5 with device XC5VLX110T. DA based FIR filter proposes advancement in speed, performance and area.